Module Standby Control Register H (Mstcrh) - Hitachi H8/3008 Hardware Manual

18.2.2

Module Standby Control Register H (MSTCRH)

MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the SCI0, SCI1.
Bit
PSTOP
Initial value
Read/Write R/W
φ clock stop
Enables or disables
output of the system clock
MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 7
PSTOP Description
0 System clock output is enabled
1 System clock output is disabled
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Reserved: This bit can be written and read.
Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1
MSTPH1 Description
0 SCI1 operates normally
1 SCI1 is in standby state
7 6
— —
0 1
— —
5 4
— —
1 1
— —
Reserved bits
3 2
— MSTPH1
1 0
R/W R/W
Module standby H1 to 0
These bits select modules
to be placed in standby
1 0
MSTPH0
0 0
R/W
(Initial value)
(Initial value)
441