Register Descriptions; System Control Register (Syscr) - Hitachi H8/3035 Series Hardware Manual

5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7
SSBY
Initial value 0
Read/Write R/W
Software standby
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as interrupt mask bit
1 UI bit in CCR is used as user bit
72
6 5 4
STS2 STS1 STS0
0 0 0
R/W R/W R/W
Standby timer
select 2 to 0
3
2
UE NMIEG
1 0
R/W R/W
Reserved bit
NMI edge select
Selects the NMI input edge
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or interrupt mask bit
1 0
— RAME
1 1
— R/W
RAM enable
(Initial value)