Internal Interrupts - Hitachi H8/3827R Series Hardware Manual

2. Interrupts IRQ to IRQ
4 0
are requested by input signals to pins IRQ to IRQ
Interrupts IRQ to IRQ . These interrupts are
4 0 4 0
detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG4 to IEG0 in IEGR.
When these pins are designated as pins IRQ to IRQ
in port mode register 3 and 1 and the
4 0
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN0
to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ to IRQ interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
4 0
numbers 8 to 4 are assigned to interrupts IRQ to IRQ . The order of priority is from IRQ (high)
4 0 0
to IRQ (low). Table 3.2 gives details.
4
3.3.4

Internal Interrupts

There are 23 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 11
are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip
peripheral modules.
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