On-Chip Peripheral Module Interrupts; Interrupt Exception Vectors And Priority Rankings - Hitachi SH7095 Hardware User Manual

5.2.4

On-chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following 6 on-chip
peripheral modules:
• Division unit (DIVU)
• Direct memory access controller (DMAC)
• Serial communications interface (SCI)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Free-running timer (FRT)
A different interrupt vector is assigned to each interrupt source, so the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers A and B (IPRA
and IPRB). On-chip peripheral module interrupt exception processing sets the interrupt mask level
bits (I3–I0) in the status register (SR) to the priority level value of the on-chip peripheral module
interrupt that was accepted.
5.2.5

Interrupt Exception Vectors and Priority Rankings

Table 5.4 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. See table 4.4, Calculating Exception Processing Vector Table Addresses
for more information on this calculation.
IRL interrupts IRL15–IRL1 have interrupt priority levels of 15–1, respectively. On-chip peripheral
module interrupt priorities can be set freely between 0 and 15 for each module by setting interrupt
priority registers A and B (IPRA and IPRB). The ranking of interrupt sources for IPRA and IPRB,
however, must be the order listed under Priority Within IPR Setting Unit in table 5.4 and cannot
be changed. A reset assigns priority level 0 to on-chip peripheral module interrupts. If the same
priority level is assigned to two or more interrupt sources and interrupts from those sources occur
simultaneously, their priority order is the default priority order indicated at the right in table 5.4.
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