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2.7.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width of each register, refer to
appendix B, Internal I/O Registers. Registers with 16-bit data bus width can be accessed by word
size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a
register with 8-bit data bus width is accessed by word size, access is completed in two cycles. In
two-state access, the operation timing is the same as that for on-chip memory.
Figure 2.12 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
ø or ø
SUB
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
Figure 2.12 On-Chip Peripheral Module Access Cycle (3-State Access)
40
T
state
1
Bus cycle
T
state
2
Address
Read data
Write data
T
state
3
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