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15.1
Overview
2
A two-channel I
C bus interface is available for the H8/3664 Series. The I
conforms to and provides a subset of the Philips I
register configuration that controls the I
however.
15.1.1
Features
• Selection of I
2
C format or synchronous serial format
I
2
C bus format: addressing format with acknowledge bit, for master/slave operation
Synchronous serial format: non-addressing format without acknowledge bit, for master
operation only
• Conforms to Philips I
• Two ways of setting slave address (I
• Start and stop conditions generated automatically in master mode (I
• Selection of acknowledge output levels when receiving (I
• Automatic loading of acknowledge bit when transmitting (I
• Wait function in master mode (I
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode (I
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
Data transfer end (including transmission mode transition with I
reception after loss of master arbitration)
Address match: when any slave address matches or the general call address is received in
slave receive mode (I
Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (with SCL and SDA pins)
Two pins—(normally NMOS push-pull outputs) function as NMOS open-drain outputs
when the bus drive function is selected.
Section 15 I
2
C bus differs partly from the Philips configuration,
2
C bus interface (I
2
C bus format)
2
C bus format)
2
C bus format)
2
C bus format)
2
C Bus Interface (IIC)
2
C bus (inter-IC bus) interface functions. The
2
C bus format)
2
C bus format)
2
C bus interface
2
C bus format)
2
C bus format)
2
C bus format and address
299
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