Other Topics; Resets; Access As Seen From The Cpu Or Dmac - Hitachi SH7095 Hardware User Manual

In standby mode or the like when synchronous DRAM and pseudo SRAM are in self-refresh
mode, memory is not precharged until the mode is cleared, so the master cannot release the bus.
Design it so the master puts the slave to sleep before self-refresh mode starts or otherwise prevent
the slave access cycle from starting, which prevents the slave from producing a bus release
request. The slave accesses these types of memories after the master finishes any processing
necessary when the self-refresh mode is cleared, such as refresh settings.
7.11

Other Topics

7.11.1

Resets

The bus state controller only does a complete initialization for a power-on reset. All signals are
immediately negated, regardless of where in the bus cycle the SH7095 is, and the output buffer is
turned off if the bus arbitration mode is slave. Signal negation is simultaneously with turning the
output buffer off. All control registers are initialized. In standby, sleep and manual reset, no bus
state controller control registers are initialized. When a manual reset is performed, any executing
bus cycles are completed, and then the SH7095 waits for an access. When a cache fill or 16-byte
DMAC transfer is executing, the CPU or DMAC that is the bus master ends the access in a
longword unit, since the access request is canceled by the manual reset. This means that when a
manual reset comes in during a cache fill, the cache contents can no longer be guaranteed. During
a manual reset, the RTCNT does not count up, so no refresh request is generated. The refresh
cycle does not start up. To preserve the data of the DRAM, synchronous DRAM or pseudo
SRAM, the pulse width of the manual reset must be shorter than the refresh interval. Master mode
chips accept arbitration requests even when a manual reset signal is asserted. When a reset has
come in only to the chip in master mode while the bus is released, the BGR signal is negated to
indicate this. If the BRLS signal is continuously asserted, the bus release state is maintained.
7.11.2

Access as Seen from the CPU or DMAC

The SH7095 is internally divided into three buses: cache, internal, and peripheral. The CPU and
cache memory are connected to the cache bus, the DMAC and bus state controller are connected
to the internal bus, and the low-speed peripherals and mode registers are connected to the
peripheral bus. The user break controller is connected to both the cache bus and the internal bus.
The internal bus can be accessed from the cache bus, but not the other way around. The peripheral
bus can be accessed from the internal bus, but not the other way around. This results in the
following.
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