Register Configuration; Data Transfer Mode Register (Dtmr); Block Diagram Of Data Transfer Controller; Internal Control Registers Of The Dtc - Hitachi H8/500 Series Hardware Manual

Interrupt controller
IRQ
0
IRQ
1
DTMR:
DTSR:
DTDR:
DTCR:
DTEA to DTED:

6.1.3 Register Configuration

The four DTC control registers are listed in table 6-1. These registers are not located in the
address space and cannot be written or read by the CPU. To set information in these registers, a
program must write the information in a table in memory from which it will be loaded by the
DTC.
Table 6-1 Internal Control Registers of the DTC
Name
Data transfer mode register
Data transfer source address register
Data transfer destination address register
Data transfer count register
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DTC request
DTEA
DTEB
DTEC
DTED
DT Mode Register
DT Source Address Register
DT Destination Address Register
DT Count Register
DT Enable Register A to D
Figure 6-1 Block Diagram of Data Transfer Controller
Internal data bus
DTC
DTMR
DTSR
DTDR
DTCR
Abbreviation
DTMR
DTSR
DTDR
DTCR
114
Register
information table
0
Register
information table
1
Read/Write
Disabled
Disabled
Disabled
Disabled
RAM