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8.4.8 DMAC Bus Cycle
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Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (T
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
CPU cycle
T
T
1
ø
Address
bus
RD
HWR
LWR
DMAC cycle (word transfer)
T
T
T
T
T
2
1
2
d
1
Source
address
Figure 8-13 DMA Transfer Bus Timing (Example)
), it reads from the source address and
d
T
T
T
T
T
2
1
2
3
1
Destination address
225
CPU cycle
T
T
T
T
T
2
3
1
2
1
2
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