Altera cyclone V Technical Reference page 3075

cv_5v4
2016.10.28
ic_clr_gen_call Fields
Bit
0
clr_gen_call
ic_enable
Enable and disable i2c operation
Module Instance
i2c0
i2c1
i2c2
i2c3
Offset:
0x6C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ic_enable Fields
Bit
1
txabort
I2C Controller
Send Feedback
Name
Read this register to clear the GEN_CALL interrupt
(bit 11) of ic_raw_intr_stat register.
0xFFC04000
0xFFC05000
0xFFC06000
0xFFC07000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Write 1 does a TX abort. Self cleared on abort
completion
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
ic_enable
Access
Register Address
0xFFC0406C
0xFFC0506C
0xFFC0606C
0xFFC0706C
21 20 19 18
5 4 3 2
Access
20-57
Reset
RO 0x0
17 16
1 0
txabo enable
rt
RW 0x0
RW
0x0
Reset
RW 0x0
Altera Corporation