Altera cyclone V Technical Reference page 3062

20-44
ic_raw_intr_stat
Bit
0
m_rx_under
ic_raw_intr_stat
Unlike the ic_intr_stat register, these bits are not masked so they always show the true status of the I2C.
Module Instance
i2c0
i2c1
i2c2
i2c3
Offset:
0x34
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
ic_raw_intr_stat Fields
Bit
11
gen_call
Altera Corporation
Name
Set if the processor attempts to read the receive buffer
when it is empty by reading from the ic_data_cmd
register. If the module is disabled ic_enable[0]=0, this
bit keeps its level until the master or slave state
machines go into idle, and then this interrupt is
cleared.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
gen_ start
call _det
RO RO
0x0 0x0
Name
Set only when a General Call address is received and
it is acknowledged. It stays set until it is cleared either
by disabling I2C or when the CPU reads bit 0 of the
ic_clr_gen_call register. I2C stores the received data
in the Rx buffer.
Description
Base Address
0xFFC04000
0xFFC05000
0xFFC06000
0xFFC07000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
stop_ activ rx_ tx_
det ity done abrt
RO RO RO RO
0x0 0x0 0x0 0x0
Description
Access
Register Address
0xFFC04034
0xFFC05034
0xFFC06034
0xFFC07034
21 20 19 18
5 4 3 2
rd_ tx_ tx_ rx_
req empty over full
RO RO RO RO
0x0 0x0 0x0 0x0
Access
cv_5v4
2016.10.28
Reset
RW 0x1
17 16
1 0
rx_ rx_under
over
RO 0x0
RO
0x0
Reset
RO 0x0
I2C Controller
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