Freescale Semiconductor MPC8250 Manuals

Manuals and User Guides for Freescale Semiconductor MPC8250. We have 1 Freescale Semiconductor MPC8250 manual available for free PDF download: Family Reference Manual

Freescale Semiconductor MPC8250 Family Reference Manual (1360 pages)

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 9 MB

Table of Contents

7
- MPC8260 Powerquicc II Family Reference Manual, Rev
  64
- Features
  76
- About this Book
  79
- Acronyms and Abbreviations
  85
  - Intended Audience
    91
  - Features
    95
  - Architecture Overview
    100
  - G2 Core
    101
  - Powerquicc II Block Diagram
    101
- Chapter 3 System Interface Unit (SIU)
  
  102
- Chapter 1 Communications Processor Module (CPM)
  
  103
  - Software Compatibility Issues
    103
    
    Signals
    104
    
    Powerquicc II External Signals
    105
  - Differences between MPC860 and Powerquicc II
    106
  - Serial Protocol Table
    106
  - Powerquicc II Configurations
    107
    
    Pin Configurations
    107
    
    Serial Performance
    107
  - Application Examples
    108
    
    Communication Systems
    108
    
    Remote Access Server
    108
    
    Remote Access Server Configuration
    109
    
    LAN-To-WAN Bridge Router
    110
    
    Regional Office Router
    110
    
    Regional Office Router Configuration
    110
    
    Cellular Base Station
    111
    
    Cellular Base Station Configuration
    111
    
    LAN-To-WAN Bridge Router Configuration
    111
    
    SONET Transmission Controller
    112
    
    Telecommunications Switch Controller
    112
    
    Telecommunications Switch Controller Configuration
    112
    
    Basic System
    113
    
    Bus Configurations
    113
    
    SONET Transmission Controller Configuration
    113
    
    Basic System Configuration
    114
    
    High-Performance Communication
    114
    
    High-Performance System Microprocessor
    115
    
    High-Performance System Microprocessor Configuration
    115
    
    PCI Configuration
    116
    
    PCI with 155-Mbps ATM
    116
    
    PCI with 155-Mbps ATM Configuration
    116
    
    Powerquicc II as PCI Agent
    117
    
    Overview
    119
    
    Powerquicc II Integrated Processor Core Block Diagram
    120
    
    Branch Processing Unit (BPU)
    123
    
    Instruction Queue and Dispatch Unit
    123
    
    Instruction Unit
    123
    
    Floating-Point Unit (FPU)
    124
    
    Independent Execution Units
    124
    
    Integer Unit (IU)
    124
    
    Load/Store Unit (LSU)
    124
    
    Completion Unit
    125
    
    Memory Management Units (Mmus)
    125
    
    Memory Subsystem Support
    125
    
    System Register Unit (SRU)
    125
    
    Cache Units
    126
    
    Programming Model
    126
    
    Register Set
    126
    
    Powerpc Register Set
    127
    
    Powerquicc II Programming Model—Registers
    128
    
    Hardware Implementation Register 0 (HID0)
    129
    
    Hardware Implementation-Dependent Register 0 (HID0)
    129
    
    Powerquicc II-Specific Registers
    129
    
    Hardware Implementation-Dependent Register 1 (HID1)
    132
    
    Hardware Implementation-Dependent Register 2 (HID2)
    132
    
    Calculating Effective Addresses
    133
    
    Powerpc Instruction Set and Addressing Modes
    133
    
    Processor Version Register (PVR)
    133
    
    Powerpc Instruction Set
    134
    
    Powerquicc II Implementation-Specific Instruction Set
    135
- Chapter 2 G2 Processor Core Features
  
  121
  - Cache Implementation
    135
    
    Data Cache
    136
    
    Powerpc Cache Model
    136
    
    Powerquicc II Implementation-Specific Cache Implementation
    136
    
    Data Cache Organization
    137
    
    Cache Locking
    138
    
    Entire Cache Locking
    138
    
    Instruction Cache
    138
    
    Way Locking
    138
  - Exception Model
    139
    
    Powerpc Exception Model
    139
    
    Powerquicc II Implementation-Specific Exception Model
    140
    
    Exception Priorities
    143
  - Memory Management
    143
    
    Powerpc MMU Model
    143
    
    Powerquicc II Implementation-Specific MMU Features
    144
    
    Instruction Timing
    145
    
    Differences between the Powerquicc II's G2 Core and the Mpc603E Microprocessor
    146
    
    SIU Block Diagram
    173
    
    System Configuration and Protection
    174
    
    Bus Monitor
    175
    
    System Configuration and Protection Logic
    175
    
    Timers Clock
    175
    
    Time Counter (TMCNT)
    176
    
    Timers Clock Generation
    176
    
    Periodic Interrupt Timer (PIT)
    177
    
    PIT Block Diagram
    177
    
    TMCNT Block Diagram
    177
    
    Software Watchdog Timer
    178
    
    Software Watchdog Timer Service State Diagram
    178
  - Interrupt Controller
    179
    
    Software Watchdog Timer Block Diagram
    179
    
    Interrupt Configuration
    180
    
    Powerquicc II Interrupt Structure
    180
    
    INT Interrupt
    181
    
    Interrupt Source Priorities
    181
    
    Machine Check Interrupt
    181
    
    SCC, FCC, and MCC Relative Priority
    184
    
    Highest Priority Interrupt
    185
    
    Masking Interrupt Sources
    185
    
    PIT, TMCNT, PCI, and IRQ Relative Priority
    185
    
    Interrupt Request Masking
    186
    
    Interrupt Vector Generation and Calculation
    186
    
    Port C External Interrupts
    188
    
    Interrupt Controller Registers
    189
    
    Programming Model
    189
    
    SIU Interrupt Configuration Register (SICR)
    189
    
    SIU Interrupt Priority Register (SIPRR)
    190
    
    CPM High Interrupt Priority Register (SCPRR_H)
    191
    
    CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
    191
    
    CPM Low Interrupt Priority Register (SCPRR_L)
    192
    
    Sipnr_H
    193
    
    SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
    193
    
    Sipnr_L
    194
    
    SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
    194
    
    Simr_H
    195
    
    Simr_L
    195
    
    SIU Interrupt Vector Register (SIVEC)
    196
    
    Interrupt Table Handling Example
    197
    
    SIU External Interrupt Control Register (SIEXR)
    197
    
    Bus Configuration Register (BCR)
    198
    
    SIU External Interrupt Control Register (SIEXR)
    198
    
    System Configuration and Protection Registers
    198
    
    Bus Configuration Register (BCR)
    199
    
    Ppc_Acr
    201
    
    X Bus Arbiter Configuration Register (PPC_ACR)
    201
    
    Ppc_Alrh
    202
    
    X Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
    202
    
    Lcl_Acr
    203
    
    Local Bus Arbiter Configuration Register (LCL_ACR)
    203
    
    Ppc_Alrl
    203
    
    Lcl_Alrh
    204
    
    Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)
    204
    
    Lcl_Alrl
    205
    
    SIU Model Configuration Register (SIUMCR)
    205
    
    SIU Module Configuration Register (SIUMCR)
    205
    
    Internal Memory Map Register (IMMR)
    208
    
    System Protection Control Register (SYPCCR)
    209
    
    Software Service Register (SWSR)
    210
    
    X Bus Transfer Error Status and Control Register 1 (TESCR1)
    210
    
    X Bus Transfer Error Status and Control Register 1 (TESCR1)
    211
    
    X Bus Transfer Error Status and Control Register 2 (TESCR2)
    212
    
    X Bus Transfer Error Status and Control Register 2 (TESCR2)
    213
    
    Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
    214
    
    Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
    215
    
    Time Counter Register (TMCNT)
    216
    
    Time Counter Status and Control Register (TMCNTSC)
    216
    
    Time Counter Alarm Register (TMCNTAL)
    217
    
    Time Counter Register (TCMCNT)
    217
    
    Periodic Interrupt Registers
    218
    
    Periodic Interrupt Status and Control Register (PISCR)
    218
    
    Periodic Interrupt Timer Count Register (PITC)
    218
    
    Periodic Interrupt Timer Count Register (PITC)
    219
    
    Periodic Interrupt Timer Register (PITR)
    219
    
    PCI Base Register (Pcibrx)
    220
    
    PCI Base Registers (Pcibrx)
    220
    
    PCI Control Registers
    220
    
    PCI Mask Register (Pcimskx)
    221
  - SIU Pin Multiplexing
    221
  - Reset Causes
    223
- Chapter 5
  
  224
  - Power-On Reset Flow
    224
  - Reset Actions
    224
  - HRESET Flow
    225
  - SRESET Flow
    225
    
    Power-On Reset Flow
    225
    
    Reset Status Register (RSR)
    226
    
    Reset Mode Register (RMR)
    227
  - Reset Configuration
    228
    
    Hard Reset Configuration Word
    230
    
    Hard Reset Configuration Examples
    232
    
    Single Chip with Default Configuration
    232
    
    Single Powerquicc II Configured from Boot EPROM
    232
    
    Single Powerquicc II with Default Configuration
    232
    
    Configuring a Single Chip from EPROM
    233
    
    Multiple Powerquicc Iis Configured from Boot EPROM
    233
    
    Configuring Multiple Chips
    234
    
    Multiple Powerquicc Iis in a System with no EPROM
    235
- Chapter 6
  
  241
  - Functional Pinout
    241
  - Signal Descriptions
    242
    
    Powerquicc II External Signals
    242
  - Signal Configuration
    258
  - Signal Descriptions
    258
    
    Signal Groupings
    258
- Chapter 7 Address Bus Arbitration Signals
  
  259
  - Address Bus Request (Br)—Input
    259
  - Address Bus Request (Br)—Output
    259
  - Bus Grant (BG)
    260
    
    Bus Grant (Bg)—Input
    260
    
    Bus Grant (Bg)—Output
    260
  - Address Bus Busy (ABB)
    261
  - Address Bus Busy (Abb)—Input
    261
  - Address Transfer Start Signal
    261
    
    Transfer Start (TS)
    261
    
    Transfer Start (Ts)—Output
    261
  - Address Transfer Signals
    262
    
    Address Bus (A[0–31])
    262
    
    Address Bus (A[0–31])—Input
    262
    
    Address Bus (A[0–31])—Output
    262
    
    Address Transfer Attribute Signals
    263
    
    Transfer Size (TSIZ[0–3])
    263
    
    Transfer Type (TT[0–4])
    263
    
    Transfer Type (Tt[0–4])—Input
    263
    
    Transfer Type (Tt[0–4])—Output
    263
    
    Caching-Inhibited (CI)—Output
    264
    
    Global (GBL)
    264
    
    Global (Gbl)—Input
    264
    
    Transfer Burst (TBST)
    264
    
    Address Acknowledge (AACK)
    265
    
    Address Acknowledge (Aack)—Input
    265
    
    Address Acknowledge (Aack)—Output
    265
    
    Address Transfer Termination Signals
    265
    
    Address Retry (ARTRY)
    266
    
    Address Retry (Artry)—Input
    266
    
    Address Retry (Artry)—Output
    266
    
    Data Bus Arbitration Signals
    267
    
    Data Bus Grant (DBG)
    267
    
    Data Bus Grant (Dbg)—Input
    267
    
    Data Bus Grant (Dbg)—Output
    267
    
    Data Bus Busy (DBB)
    268
    
    Data Bus Busy (Dbb)—Input
    268
    
    Data Bus Busy (Dbb)—Output
    268
  - Data Transfer Signals
    268
    
    Data Bus (D[0–63])—Input
    269
    
    Data Bus Parity (DP[0–7])
    269
    
    Data Bus Parity (Dp[0–7])—Output
    269
  - Data Transfer Termination Signals
    270
    
    Transfer Acknowledge (TA)
    270
    
    Transfer Acknowledge (Ta)—Input
    270
    
    Transfer Acknowledge (Ta)—Output
    271
  - Partial Data Valid (Psdval)—Input
    272
  - Partial Data Valid Indication (PSDVAL)
    272
  - Transfer Error Acknowledge (TEA)
    272
    
    Transfer Error Acknowledge (Tea)—Output
    272
    
    Partial Data Valid (Psdval)—Output
    273
- Chapter 8
  
  275
  - Terminology
    275
    
    Bus Configuration
    276
    
    Single-Powerquicc II Bus Mode
    276
    
    Single-Powerquicc II Bus Mode
    277
    
    X-Compatible Bus Mode
    277
  - X Bus Protocol Overview
    278
    
    X-Compatible Bus Mode
    278
    
    Arbitration Phase
    279
    
    Basic Transfer Protocol
    279
    
    Address Pipelining and Split-Bus Transactions
    280
  - Address Tenure Operations
    281
    
    Address Arbitration
    281
    
    Address Bus Arbitration with External Bus Master
    282
    
    Address Pipelining
    282
    
    Address Pipelining
    283
    
    Address Transfer Attribute Signals
    283
    
    Transfer Type Signal (TT[0–4]) Encoding
    283
    
    TBST and TSIZ[0–3] Signals and Size of Transfer
    286
    
    Transfer Code Signals TC[0–2]
    286
    
    Burst Ordering During Data Transfers
    287
    
    Effect of Alignment on Data Transfers
    288
    
    Effect of Port Size on Data Transfers
    290
    
    Interface to Different Port Size Devices
    291
    
    X-Compatible Bus Mode—Size Calculation
    292
    
    Extended Transfer Mode
    293
    
    Address Retried with ARTRY
    296
    
    Address Transfer Termination
    296
    
    Retry Cycle
    297
    
    Address Tenure Timing Configuration
    298
    
    Pipeline Control
    298
  - Data Tenure Operations
    299
    
    Data Bus Arbitration
    299
    
    Data Bus Transfers and Normal Termination
    300
    
    Data Streaming Mode
    300
    
    Effect of ARTRY Assertion on Data Transfer and Arbitration
    301
    
    Port Size Data Bus Transfers and PSDVAL Termination
    301
    
    Single-Beat and Burst Data Transfers
    301
    
    Bit Extended Transfer to 32-Bit Port Size
    302
    
    Burst Transfer to 32-Bit Port Size
    303
    
    Data Bus Termination by Assertion of TEA
    303
    
    Data Tenure Terminated by Assertion of TEA
    304
    
    Memory Coherency—Mei Protocol
    304
  - Processor State Signals
    305
    
    MEI Cache Coherency Protocol—State Diagram (WIM = 001)
    305
    
    Support for the Lwarx/Stwcx. Instruction Pair
    306
    
    TLBISYNC Input
    306
  - Little-Endian Mode
    306
    
    PCI Bridge in the Powerquicc II
    308
    
    PCI Bridge Structure
    308
- Chapter 9
  
  309
  - Clocking
    309
    
    Signals
    309
  - PCI Bridge Initialization
    309
    
    SDMA Interface
    309
  - Interrupts from PCI Bridge
    310
  - X Bus Arbitration Priority
    310
  - X Bus Masters
    310
  - Compactpci Hot Swap Specification Support
    311
    
    PCI Interface
    311
    
    Bus Commands
    312
    
    PCI Interface Operation
    312
    
    PCI Protocol Fundamentals
    313
    
    Addressing
    314
    
    Basic Transfer Control
    314
    
    Bus Driving and Turnaround
    315
    
    Bus Transactions
    315
    
    Byte Enable Signals
    315
    
    Read and Write Transactions
    315
    
    Burst Read Example
    316
    
    Single Beat Read Example
    316
    
    Burst Write Example
    317
    
    Single Beat Write Example
    317
    
    Transaction Termination
    317
    
    Target-Initiated Terminations
    318
    
    Device Selection
    319
    
    Other Bus Operations
    319
    
    Data Streaming
    320
    
    Fast Back-To-Back Transactions
    320
    
    Host Mode Configuration Access
    321
    
    PCI Configuration Type 0 Translation (Top = CONFIG_ADDR Bottom = PCI Address Lines)
    321
    
    Agent Mode Configuration Access
    322
    
    Special Cycle Command
    322
    
    Error Functions
    323
    
    Interrupt Acknowledge
    323
    
    Parity
    323
    
    Error Reporting
    324
    
    PCI Parity Operation
    324
    
    Arbitration Algorithm
    325
    
    Bus Parking
    325
    
    PCI Bus Arbitration
    325
    
    Master Latency Timer
    326
    
    PCI Arbitration Example
    326
    
    Address Decode Flow Chart for 60X Bus Mastered Transactions
    327
    
    Address Map
    327
    
    Address Decode Flow Chart for PCI Mastered Transactions
    328
    
    Address Map Example
    330
    
    Address Map Programming
    330
    
    Address Translation
    330
    
    Inbound PCI Memory Address Translation
    331
    
    PCI Inbound Translation
    331
    
    Outbound PCI Memory Address Translation
    332
    
    PCI Outbound Translation
    332
    
    SIU Registers
    332
  - Configuration Registers
    333
    
    Memory-Mapped Configuration Registers
    333
    
    DMA Controller Registers
    336
    
    PCI Outbound Translation Address Registers (Potarx)
    336
    
    PCI Outbound Base Address Registers (Pobarx)
    337
    
    PCI Outbound Comparison Mask Registers (Pocmrx)
    337
    
    Discard Timer Control Register (PTCR)
    338
    
    PCI Outbound Comparison Mask Registers (Pocmrx)
    338
    
    Discard Timer Control Register (PTCR)
    339
    
    General Purpose Control Register (GPCR)
    339
    
    General Purpose Control Register (GPCR)
    340
    
    Error Status Register (ESR)
    341
    
    PCI General Control Register (PCI_GCR)
    341
    
    Error Status Register (ESR)
    342
    
    Error Mask Register (EMR)
    343
    
    Error Control Register (ECR)
    344
    
    PCI Error Address Capture Register (PCI_EACR)
    345
    
    PCI Error Control Capture Register (PCI_ECCR)
    346
    
    PCI Error Data Capture Register (PCI_EDCR)
    346
    
    PCI Error Control Capture Register (PCI_ECCR)
    347
    
    PCI Inbound Base Address Registers (Pibarx)
    348
    
    PCI Inbound Translation Address Registers (Pitarx)
    348
    
    PCI Inbound Base Address Registers (Pibarx)
    349
    
    PCI Inbound Comparison Mask Registers (Picmrx)
    349
    
    PCI Inbound Comparison Mask Registers (Picmrx)
    350
  - PCI Bridge Configuration Registers
    351
    
    PCI Bridge PCI Configuration Registers
    352
    
    Vendor ID Register
    352
    
    Device ID Register
    353
    
    PCI Bus Command Register
    353
    
    Vendor ID Register
    353
    
    PCI Bus Status Register
    354
    
    PCI Bus Status Register
    355
    
    Revision ID Register
    355
    
    PCI Bus Programming Interface Register
    356
    
    Revision ID Register
    356
    
    Subclass Code Register
    356
    
    PCI Bus Base Class Code Register
    357
    
    PCI Bus Cache Line Size Register
    357
    
    Subclass Code Register
    357
    
    Header Type Register
    358
    
    PCI Bus Cache Line Size Register
    358
    
    PCI Bus Latency Timer Register
    358
    
    BIST Control Register
    359
    
    Header Type Register
    359
    
    PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)
    359
    
    General Purpose Local Access Base Address Registers (Gplabarx)
    360
    
    PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR)
    360
    
    General Purpose Local Access Base Address Registers (Gplabarx)
    361
    
    Subsystem Vendor ID Register
    361
    
    PCI Bus Capabilities Pointer Register
    362
    
    PCI Bus Interrupt Line Register
    362
    
    Subsystem Device ID Register
    362
    
    PCI Bus Interrupt Line Register
    363
    
    PCI Bus Interrupt Pin Register
    363
    
    PCI Bus MIN GNT
    363
    
    PCI Bus Function Register
    364
    
    PCI Bus MAX LAT
    364
    
    PCI Bus Arbiter Configuration Register
    365
  - PCI Hot Swap Register Block
    366
  - PCI Hot Swap Control Status Register
    367
  - PCI Configuration Register Access from the Core
    368
    
    PCI Configuration Register Access in Big-Endian Mode
    368
    
    Additional Information on Endianess
    369
    
    Notes on GPCR[LE_MODE]
    369
    
    Data Structure for Register Initialization
    370
    
    Initializing the PCI Configuration Registers
    370
    
    Message Registers
    371
    
    PCI Configuration Data Structure for the EEPROM
    371
    
    Inbound Message Registers (Imrx)
    372
    
    Outbound Message Registers (Omrx)
    372
    
    Door Bell Registers
    373
    
    Outbound Doorbell Register (ODR)
    373
    
    Outbound Message Registers (Omrx)
    373
    
    Inbound Doorbell Register (IDR)
    374
    
    Outbound Doorbell Register (ODR)
    374
    
    Inbound Fifos
    376
    
    PCI Configuration Identification
    376
    
    Inbound Free_Fifo Head Pointer Register (IFHPR)
    377
    
    Inbound Free_Fifo Head Pointer Register (IFHPR) and Inbound Free_Fifo Tail Pointer Register (IFTPR)
    377
    
    Inbound Free_Fifo Tail Pointer Register (IFTPR)
    378
    
    Inbound Post_Fifo Head Pointer Register (IPHPR) and Inbound Post_Fifo Tail Pointer Register (IPTPR)
    378
    
    Inbound Post_Fifo Head Pointer Register (IPHPR)
    379
    
    Inbound Post_Fifo Tail Pointer Register (IPTPR)
    379
    
    Outbound Fifos
    380
    
    Outbound Free_Fifo Head Pointer Register (OFHPR)
    380
    
    Outbound Free_Fifo Head Pointer Register (OFHPR) and Outbound Free_Fifo Tail Pointer Register (OFTPR)
    380
    
    Outbound Free_Fifo Tail Pointer Register (OFTPR)
    381
    
    Outbound Post_Fifo Head Pointer Register (OPHPR) and Outbound Post_Fifo Tail Pointer Register (OPTPR)
    381
    
    Outbound Post_Fifo Head Pointer Register (OPHPR)
    382
    
    Inbound FIFO Queue Port Register (IFQPR)
    383
    
    Outbound Post_Fifo Tail Pointer Register (OPTPR)
    383
    
    Outbound FIFO Queue Port Register (OFQPR)
    384
    
    Outbound Message Interrupt Status Register (OMISR)
    384
    
    Outbound Message Interrupt Mask Register (OMIMR)
    385
    
    Outbound Message Interrupt Status Register (OMISR)
    385
    
    Inbound Message Interrupt Status Register (IMISR)
    386
    
    Outbound Message Interrupt Mask Register (OMIMR)
    386
    
    Inbound Message Interrupt Status Register (IMISR)
    387
    
    Inbound Message Interrupt Mask Register (IMIMR)
    388
    
    Messaging Unit Control Register (MUCR)
    389
    
    Queue Base Address Register (QBAR)
    390
  - DMA Controller
    391
    
    DMA Controller Block Diagram
    391
    
    DMA Operation
    391
    
    DMA Chaining Mode
    392
    
    DMA Direct Mode
    392
    
    DMA Coherency
    393
    
    DMA Transfer Types
    393
    
    Halt and Error Conditions
    393
    
    DMA Mode Register [0–3] (Dmamrx)
    394
    
    DMA Registers
    394
    
    DMA Status Register [0–3] (Dmasrx)
    396
    
    DMA Current Descriptor Address Register [0–3] (Dmacdarx)
    397
    
    DMA Destination Address Register [0–3] (Dmadarx)
    398
    
    DMA Source Address Register [0–3] (Dmasarx)
    398
    
    DMA Byte Count Register [0–3] (Dmabcrx)
    399
    
    DMA Destination Address Register [0–3] (Dmadarx)
    399
    
    DMA Next Descriptor Address Register [0–3] (Dmandarx)
    400
    
    DMA Segment Descriptors
    401
    
    Descriptor in Big Endian Mode
    402
    
    DMA Chain of Segment Descriptors
    402
    
    Descriptor in Little Endian Mode
    403
  - Error Handling
    403
    
    Interrupt and Error Signals
    403
    
    PCI Bus Error Signals
    403
    
    Error Reporting
    404
    
    Illegal Register Access Error
    404
    
    Parity Error (Perr)
    404
    
    PCI Interface
    404
    
    System Error (Serr)
    404
    
    Address Parity Error
    405
    
    Data Parity Error
    405
    
    Master-Abort Transaction Termination
    405
    
    Embedded Utilities
    406
    
    Inbound Doorbell Machine Check
    406
    
    Inbound Post Queue Overflow
    406
    
    Outbound Free Queue Overflow
    406
    
    Target-Abort Error
    406
- Chapter 10
  
  407
  - Clock Configuration
    407
  - Clock Unit
    407
  - External Clock Inputs
    407
  - Main PLL
    408
    
    PLL Block Diagram
    408
    
    System PLL Block Diagram
    408
    
    PCI Bridge as an Agent Operating from the PCI System Clock
    409
    
    PCI Bridge Clocking
    409
    
    Skew Elimination
    409
    
    PCI Bridge as a Host and Generating the PCI System Clock
    410
    
    PCI Bridge as a Host, Generating the PCI System Clock
    410
    
    PCI Bridge as an Agent, Operating from the PCI System Clock
    410
    
    CPM CLOCK and PCI Frequency Equations
    411
  - Clock Dividers
    411
  - Powerquicc II Internal Clock Signals
    411
    
    General System Clocks
    411
  - PLL Pins
    412
    
    PLL Filtering Circuit
    413
    
    System Clock Control Register (SCCR)
    414
    
    System Clock Mode Register (SCMR)
    415
    
    Relationships of SCMR Parameters
    416
  - Basic Power Structure
    417
- Chapter 11 Memory Controller
  
  419
- Chapter 12
  
  525
  - Copy-Back Mode
    525
  - L2 Cache in Copy-Back Mode
    526
  - Write-Through Mode
    526
  - Ecc/Parity Mode
    528
  - External L2 Cache in Write-Through Mode
    528
  - L2 Cache Interface Parameters
    530
    
    External L2 Cache in Ecc/Parity Mode
    530
  - L2 Cache Operation
    531
  - System Requirements When Using the L2 Cache Interface
    531
  - Timing Example
    531
    
    Read Access with L2 Cache
    532
    
    Overview
    533
    
    TAP Controller
    534
    
    Test Logic Block Diagram
    534
    
    Boundary Scan Register
    535
    
    TAP Controller State Machine
    535
    
    Observe-Only Input Pin Cell (I.obs)
    536
    
    Output Pin Cell (O.pin)
    536
    
    General Arrangement of Bidirectional Pin Cells
    537
    
    Instruction Register
    537
    
    Output Control Cell (IO.CTL)
    537
- Chapter 13 Powerquicc II Restrictions
  
  539
  - Nonscan Chain Operation
    539
- Chapter 14 Communications Processor Module
  
  541
  - Features
    549
  - Powerquicc II Serial Configurations
    551
    
    Powerquicc II CPM Block Diagram
    551
    
    Communications Processor (CP)
    552
    
    CPM Performance Evaluation
    552
    
    Features
    552
    
    CP Block Diagram
    553
    
    Communications Processor (CP) Block Diagram
    554
    
    G2 Core Interface
    554
    
    Peripheral Interface
    555
    
    Execution from RAM
    556
    
    RISC Controller Configuration Register (RCCR)
    556
    
    RISC Controller Configuration Register (RCCR
    557
    
    RISC Time-Stamp Control Register (RTSCR)
    559
    
    RISC Time-Stamp Register (RTSR)
    559
    
    RISC Microcode Revision Number
    560
  - Command Set
    560
    
    RISC Time-Stamp Register (RTSR)
    560
    
    CP Command Register (CPCR)
    561
    
    CP Commands
    562
    
    Command Execution Latency
    565
    
    Command Register Example
    565
  - Dual-Port RAM
    565
    
    Dual-Port RAM Block Diagram
    566
    
    Dual-Port RAM Memory Map
    567
    
    Buffer Descriptors (Bds)
    568
    
    Parameter RAM
    568
    
    RISC Timer Table Parameter RAM
    570
    
    RISC Timer Tables
    570
    
    RISC Timer Table RAM Usage
    571
    
    RISC Timer Command Register (TM_CMD)
    572
    
    RISC Timer Event Register (Rter)/Mask Register (RTMR)
    572
    
    RISC Timer Table Entries
    572
    
    RISC Timer Event Register (Rter)/Mask Register (RTMR)
    573
    
    RISC Timer Initialization Sequence
    573
    
    RISC Timer Initialization Example
    574
    
    RISC Timer Interrupt Handling
    574
    
    RISC Timer Table Scan Algorithm
    574
    
    Using the RISC Timers to Track CP Loading
    575
    
    SI Block Diagram
    578
    
    Features
    579
    
    Overview
    580
    
    Various Configurations of a Single TDM Channel
    581
    
    Dual TDM Channel Example
    582
- Chapter 15
  
  583
  - Enabling Connections to TSA
    583
  - Serial Interface RAM
    584
    
    Enabling Connections to the TSA
    584
    
    One Multiplexed Channel with Dynamic Frames
    585
    
    One Multiplexed Channel with Static Frames
    585
    
    One TDM Channel with Static Frames and Independent Rx and Tx Routes
    585
    
    One TDM Channel with Shadow RAM for Dynamic Route Change
    586
    
    Programming Six RAM Entries
    586
    
    Six RAM Entry Fields
    586
    
    Using the SWTR Feature
    588
    
    Six RAM Programming Example
    590
    
    Static and Dynamic Routing
    590
    
    Example: Six RAM Dynamic Changes, Tdma and B, same Six RAM Size
    592
  - Serial Interface Registers
    593
    
    SI Global Mode Registers (Sixgmr)
    593
    
    SI Mode Registers (Sixmr)
    593
    
    SI Mode Registers (Sixmr)
    594
    
    No Delay from Sync to Data (Xfsd = 00)
    596
    
    One-Clock Delay from Sync to Data (Xfsd = 01)
    596
    
    Falling Edge (FE) Effect When CE = 0 and Xfsd = 01
    597
    
    Falling Edge (FE) Effect When CE = 1 and Xfsd = 01
    597
    
    Falling Edge (FE) Effect When CE = 1 and Xfsd = 00
    598
    
    Falling Edge (FE) Effect When CE = 0 and Xfsd = 00
    599
    
    Six RAM Shadow Address Registers (Sixrsr)
    599
    
    SI Command Register (Sixcmdr)
    600
    
    Six RAM Shadow Address Registers (Sixrsr)
    600
    
    SI Status Registers (Sixstr)
    601
  - Serial Interface IDL Interface Support
    601
    
    Dual IDL Bus Application Example
    602
    
    IDL Interface Example
    602
    
    IDL Terminal Adaptor
    603
    
    IDL Bus Signals
    604
    
    IDL Interface Programming
    605
  - Serial Interface GCI Support
    606
    
    GCI Bus Signals
    607
    
    Normal Mode GCI Programming
    608
    
    Serial Interface GCI Programming
    608
    
    SI GCI Activation/Deactivation Procedure
    608
    
    SCIT Programming
    609
    
    CPM Multiplexing Logic (CMX) Block Diagram
    612
    
    Features
    612
- Chapter 16
  
  613
  - Enabling Connections to TSA or NMSI
    613
  - NMSI Configuration
    614
    
    Enabling Connections to the TSA
    614
    
    Bank of Clocks
    615
  - CMX Registers
    617
    
    CMX UTOPIA Address Register (CMXUAR)
    617
    
    Connection of the Master Address
    619
    
    Connection of the Slave Address
    619
    
    Multi-PHY Receive Address Multiplexing
    621
    
    CMX SI1 Clock Route Register (CMXSI1CR)
    622
    
    CMX SI2 Clock Route Register (CMXSI2CR)
    622
    
    CMX FCC Clock Route Register (CMXFCR)
    623
    
    CMX SI2 Clock Route Register (CMXSI2CR)
    623
    
    CMX FCC Clock Route Register (CMXFCR)
    624
    
    CMX SCC Clock Route Register (CMXSCR)
    626
    
    CMX SMC Clock Route Register (CMXSMR)
    629
    
    Baud-Rate Generator (BRG) Block Diagram
    631
- Chapter 17
  
  632
  - BRG Configuration Registers 1–8 (Brgcx)
    632
    
    Baud-Rate Generator Configuration Registers (Brgcx)
    632
  - Autobaud Operation on a UART
    634
  - UART Baud Rate Examples
    635
    
    Features
    637
    
    Timer Block Diagram
    637
  - General-Purpose Timer Units
    638
- Chapter 18
  
  639
- Chapter 19
  
  646
  - SDMA Bus Arbitration and Bus Transfers
    646
  - SDMA Registers
    647
    
    SDMA Bus Arbitration (Transaction Steal)
    647
    
    SDMA Status Register (SDSR)
    647
    
    SDMA Mask Register (SDMR)
    648
    
    SDMA Transfer Error Address Registers (PDTEA and LDTEA)
    648
    
    SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM)
    648
  - IDMA Emulation
    649
  - IDMA Features
    649
  - IDMA Transfers
    650
    
    Memory-To-Memory Transfers
    650
    
    IDMA Transfer Buffer in the Dual-Port RAM
    651
    
    External Request Mode
    652
    
    Memory To/From Peripheral Transfers
    653
    
    Normal Mode
    653
    
    Working with a PCI Bus
    653
    
    Dual-Address Transfers
    654
    
    Memory to Peripheral
    654
    
    Peripheral to Memory
    654
    
    Controlling 60X Bus Bandwidth
    655
    
    Memory-To-Peripheral Fly-By Transfers
    655
    
    Peripheral-To-Memory Fly-By Transfers
    655
    
    PCI Burst Length and Latency Control
    656
  - IDMA Interface Signals
    657
    
    Dreqx and Dackx
    657
    
    Level-Sensitive Mode
    658
    
    Donex
    659
    
    Edge-Sensitive Mode
    659
    
    Timing Requirement for DREQ Negation When IMDA Read from a Peripheral
    659
  - IDMA Priorities
    657
  - IDMA Operation
    660
    
    Auto Buffer and Buffer Chaining
    660
    
    Idmax Channel's BD Table
    661
    
    Idmax Parameter RAM
    661
    
    DCM Parameters
    663
    
    DMA Channel Mode (DCM)
    663
    
    Data Transfer Types as Programmed in DCM
    665
    
    Programming DTS and STS
    666
    
    IDMA Performance
    667
    
    IDMA Bds
    668
    
    IDMA Event Register (IDSR) and Mask Register (IDMR)
    668
    
    IDMA Event/Mask Registers (IDSR/IDMR)
    668
    
    IDMA BD Structure
    669
  - IDMA Commands
    671
  - IDMA Bus Exceptions
    672
    
    Externally Recognizing IDMA Operand Transfers
    673
  - Programming the Parallel I/O Registers
    673
  - IDMA Programming Examples
    674
    
    Memory-To-Peripheral Fly-By Mode—Idma3
    676
    
    Memory-To-Memory (PCI Bus to 60X Bus)—Idma1
    677
    
    Features
    680
    
    SCC Block Diagram
    680
- Chapter 20 The General SCC Mode Registers (GSMR1–GSMR4)
  
  681
  - Gsmr_H—General SCC Mode Register (High Order)
    681
  - Gsmr_L—General SCC Mode Register (Low Order)
    683
  - Data Synchronization Register (DSR)
    687
  - Protocol-Specific Mode Register (PSMR)
    687
  - SCC Buffer Descriptors (Bds)
    688
    
    Transmit-On-Demand Register (TODR)
    688
    
    SCC Buffer Descriptors (Bds)
    689
  - SCC BD and Buffer Memory Structure
    690
  - SCC Parameter RAM
    691
    
    SCC Base Addresses
    692
    
    Function Code Registers (RFCR and TFCR)
    693
    
    Handling SCC Interrupts
    694
    
    Controlling SCC Timing with RTS, CTS, and CD
    695
    
    Initializing the Sccs
    695
    
    Synchronous Protocols
    695
    
    Output Delay from CTS Asserted for Synchronous Protocols
    696
    
    Output Delay from RTS Asserted for Synchronous Protocols
    696
    
    CTS Lost in Synchronous Protocols
    697
    
    Asynchronous Protocols
    698
    
    Using CD to Control Synchronous Protocol Reception
    698
    
    Digital Phase-Locked Loop (DPLL) Operation
    699
    
    DPLL Receiver Block Diagram
    699
    
    DPLL Transmitter Block Diagram
    700
    
    DPLL Encoding Examples
    701
    
    Encoding Data with a DPLL
    701
    
    General Reconfiguration Sequence for an SCC Transmitter
    702
    
    Reconfiguring the Sccs
    702
    
    General Reconfiguration Sequence for an SCC Receiver
    703
    
    Reset Sequence for an SCC Receiver
    703
    
    Reset Sequence for an SCC Transmitter
    703
    
    Saving Power
    703
    
    Switching Protocols
    703
    
    UART Character Format
    705
- Chapter 21
  
  706
  - Normal Asynchronous Mode
    706
    
    Features
    706
  - SCC UART Parameter RAM
    707
  - Synchronous Mode
    707
  - Data-Handling Methods: Character- or Message-Based
    709
  - Error and Status Reporting
    709
  - Multidrop Systems and Address Recognition
    710
  - SCC UART Commands
    710
  - Receiving Control Characters
    711
    
    Two UART Multidrop Configurations
    711
    
    Control Character Table
    712
  - Hunt Mode (Receiver)
    713
  - Inserting Control Characters into the Transmit Data Stream
    713
    
    Transmit Out-Of-Sequence Register (TOSEQ)
    713
  - Fractional Stop Bits (Transmitter)
    714
    
    Asynchronous UART Transmitter
    714
  - Sending a Break (Transmitter)
    714
  - Sending a Preamble (Transmitter)
    714
  - Handling Errors in the SCC UART Controller
    715
  - UART Mode Register (PSMR)
    716
    
    Protocol-Specific Mode Register for UART (PSMR)
    717
    
    SCC UART Receive Buffer Descriptor (Rxbd)
    718
    
    SCC UART Receiving Using Rxbds
    720
    
    SCC UART Receive Buffer Descriptor (Rxbd)
    721
    
    SCC UART Transmit Buffer Descriptor (Txbd)
    722
    
    SCC UART Event Register (SCCE) and Mask Register (SCCM)
    723
    
    SCC UART Event Register (SCCE) and Mask Register (SCCM)
    724
    
    SCC UART Interrupt Event Example
    724
  - SCC UART Status Register (SCCS)
    725
    
    SCC Status Register for UART Mode (SCCS)
    725
  - SCC UART Programming Example
    726
  - S-Records Loader Application
    727
- Chapter 22
  
  729
  - SCC HDLC Features
    729
  - SCC HDLC Channel Frame Reception
    730
    
    HDLC Framing Structure
    730
  - SCC HDLC Channel Frame Transmission
    730
  - SCC HDLC Parameter RAM
    731
  - Programming the SCC in HDLC Mode
    732
    
    HDLC Address Recognition
    732
  - Handling Errors in the SCC HDLC Controller
    733
    
    HDLC Mode Register (PSMR)
    735
    
    SCC HDLC Receive Buffer Descriptor (Rxbd)
    736
    
    SCC HDLC Receiving Using Rxbds
    738
    
    SCC HDLC Transmit Buffer Descriptor (Txbd)
    739
    
    HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
    740
    
    SCC HDLC Interrupt Event Example
    741
  - SCC HDLC Commands
    733
  - SCC HDLC Programming Example #1
    742
    
    SCC HDLC Programming Example #2
    744
  - SCC HDLC Programming Examples
    742
  - SCC HDLC Status Register (SCCS)
    742
  - HDLC Bus Mode with Collision Detection
    744
    
    Typical HDLC Bus Multimaster Configuration
    745
    
    Accessing the HDLC Bus
    746
    
    HDLC Bus Features
    746
    
    Typical HDLC Bus Single-Master Configuration
    746
    
    Detecting an HDLC Bus Collision
    747
    
    Increasing Performance
    747
    
    Delayed RTS Mode
    748
    
    HDLC Bus Transmission Line Configuration
    748
    
    Nonsymmetrical Tx Clock Duty Cycle for Increased Performance
    748
    
    Delayed RTS Mode
    749
    
    HDLC Bus TDM Transmission Line Configuration
    749
    
    Using the Time-Slot Assigner (TSA)
    749
    
    HDLC Bus Controller Programming Example
    750
    
    HDLC Bus Protocol Programming
    750
    
    Programming GSMR and PSMR for the HDLC Bus Protocol
    750
    
    Classes of BISYNC Frames
    751
- Chapter 23
  
  752
  - SCC BISYNC Channel Frame Transmission
    752
    
    Features
    752
  - SCC BISYNC Channel Frame Reception
    753
  - SCC BISYNC Parameter RAM
    753
  - SCC BISYNC Commands
    754
  - SCC BISYNC Control Character Recognition
    755
    
    Control Character Table and RCCM
    756
  - BISYNC SYNC Register (BSYNC)
    757
  - SCC BISYNC DLE Register (BDLE)
    758
    
    Bisync Dle (Bdle)
    758
  - Handling Errors in the SCC BISYNC
    759
  - Sending and Receiving the Synchronization Sequence
    759
  - BISYNC Mode Register (PSMR)
    760
    
    Protocol-Specific Mode Register for BISYNC (PSMR)
    760
  - SCC BISYNC Receive BD (Rxbd)
    762
    
    SCC BISYNC Rxbd
    762
    
    SCC BISYNC Transmit BD (Txbd)
    764
    
    BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
    765
    
    BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
    766
    
    SCC Status Registers (SCCS)
    766
  - Programming the SCC BISYNC Controller
    767
  - SCC BISYNC Programming Example
    768
    
    Features
    771
- Chapter 24
  
  772
- Chapter 25
  
  785
  - Ethernet on the Powerquicc II
    785
    
    Ethernet Frame Structure
    785
    
    Ethernet Block Diagram
    786
    
    Features
    786
    
    Connecting the Powerquicc II to Ethernet
    788
  - SCC Ethernet Channel Frame Transmission
    789
  - SCC Ethernet Channel Frame Reception
    790
  - The Content-Addressable Memory (CAM) Interface
    790
  - SCC Ethernet Parameter RAM
    791
  - Programming the Ethernet Controller
    793
  - SCC Ethernet Commands
    793
    
    Programming Example
    794
  - SCC Ethernet Address Recognition
    795
    
    Ethernet Address Recognition Flowchart
    795
  - Handling Collisions
    796
  - Hash Table Algorithm
    796
  - Interpacket Gap Time
    796
  - Full-Duplex Ethernet Support
    797
  - Handling Errors in the Ethernet Controller
    797
    
    Ethernet Mode Register (PSMR)
    798
  - Internal and External Loopback
    797
  - SCC Ethernet Receive BD
    800
    
    SCC Ethernet Rxbd
    800
  - SCC Ethernet Transmit Buffer Descriptor
    802
    
    Ethernet Receiving Using Rxbds
    802
    
    SCC Ethernet Txbd
    803
    
    SCC Ethernet Event Register (Scce)/Mask Register (SCCM)
    804
    
    Ethernet Interrupt Events Example
    805
  - SCC Ethernet Programming Example
    806
  - Operating the Localtalk Bus
    809
- Chapter 26 SCC Appletalk Mode
  
  809
  - Localtalk Frame Format
    809
  - Connecting to Appletalk
    810
    
    Features
    810
  - Programming the SCC in Appletalk Mode
    811
    
    Connecting the Powerquicc II to Localtalk
    811
    
    Programming the GSMR
    811
    
    Programming the PSMR
    812
    
    Programming the TODR
    812
    
    SCC Appletalk Programming Example
    812
    
    SMC Block Diagram
    813
- Chapter 27 Common SMC Settings and Configurations
  
  814
  - Features
    814
  - SMC Mode Registers (SMCMR1/SMCMR2)
    814
  - SMC Mode Registers (SMCMR1/SMCMR2)
    815
  - SMC Buffer Descriptor Operation
    816
  - SMC Memory Structure
    817
  - SMC Parameter RAM
    817
  - Disabling Smcs On-The-Fly
    820
    
    SMC Receiver Full Sequence
    821
    
    SMC Receiver Shortcut Sequence
    821
    
    SMC Transmitter Full Sequence
    821
    
    SMC Transmitter Shortcut Sequence
    821
    
    Switching Protocols
    821
    
    Saving Power
    822
  - SMC Function Code Registers (RFCR/TFCR)
    820
  - Handling Interrupts in the SMC
    822
  - SMC in UART Mode
    822
    
    SMC UART Frame Format
    822
    
    Features
    823
    
    Programming the SMC UART Controller
    823
    
    SMC UART Channel Reception Process
    823
    
    SMC UART Channel Transmission Process
    823
    
    Sending a Break
    824
    
    SMC UART Transmit and Receive Commands
    824
    
    Handling Errors in the SMC UART Controller
    825
    
    Sending a Preamble
    825
    
    SMC UART Rxbd
    825
    
    SMC UART Rxbd
    826
    
    Rxbd Example
    828
    
    SMC UART Txbd
    829
    
    SMC UART Event Register (Smce)/Mask Register (SMCM)
    830
    
    SMC UART Controller Programming Example
    831
    
    SMC UART Interrupts Example
    831
  - SMC in Transparent Mode
    832
    
    Features
    832
    
    SMC Transparent Channel Reception Process
    833
    
    SMC Transparent Channel Transmission Process
    833
    
    Using SMSYN for Synchronization
    834
    
    Synchronization with Smsynx
    835
    
    Using the Time-Slot Assigner (TSA) for Synchronization
    835
    
    Synchronization with the TSA
    836
    
    Handling Errors in the SMC Transparent Controller
    837
    
    SMC Transparent Commands
    837
    
    SMC Transparent Rxbd
    838
    
    SMC Transparent Txbd
    839
    
    SMC Transparent Event Register (Smce)/Mask Register (SMCM)
    840
    
    SMC Transparent Event Register (Smce)/Mask Register (SMCM)
    841
    
    SMC Transparent NMSI Programming Example
    841
  - The SMC in GCI Mode
    842
    
    SMC GCI Parameter RAM
    842
    
    Handling the GCI Monitor Channel
    843
    
    SMC GCI Monitor Channel Reception Process
    843
    
    SMC GCI Monitor Channel Transmission Process
    843
    
    Handling the GCI C/I Channel
    844
    
    SMC GCI C/I Channel Reception Process
    844
    
    SMC GCI C/I Channel Transmission Process
    844
    
    SMC GCI Commands
    844
    
    SMC GCI Monitor Channel Rxbd
    844
    
    SMC Monitor Channel Rxbd
    844
    
    SMC GCI C/I Channel Rxbd
    845
    
    SMC GCI Monitor Channel Txbd
    845
    
    SMC Monitor Channel Txbd
    845
    
    SMC C/I Channel Rxbd
    846
    
    SMC C/I Channel Txbd
    846
    
    SMC GCI C/I Channel Txbd
    846
    
    SMC GCI Event Register (Smce)/Mask Register (SMCM)
    846
    
    SMC GCI Event Register (Smce)/Mask Register (SMCM)
    847
  - MCC Operation Overview
    850
- Chapter 28 MCC Data Structure Organization
  
  850
  - BD Structure for One MCC
    851
  - Global MCC Parameters
    852
  - Channel-Specific Parameters
    853
    
    Channel-Specific HDLC Parameters
    853
    
    Internal Transmitter State (TSTATE)—HDLC Mode
    855
    
    TSTATE High Byte
    855
    
    Channel Mode Register (CHAMR)
    856
    
    Channel Mode Register (CHAMR)—HDLC Mode
    856
    
    INTMSK Mask Bits
    856
    
    Internal Receiver State (RSTATE)—HDLC Mode
    858
    
    Rx Internal State (RSTATE) High Byte
    858
    
    Channel-Specific Transparent Parameters
    859
    
    Interrupt Mask (Intmsk)—Transparent Mode
    860
    
    Channel Mode Register (Chamr)—Transparent Mode
    861
    
    Internal Receiver State (Rstate)—Transparent Mode
    862
    
    MCC Parameters for AAL1 CES Usage
    862
    
    Channel-Specific Parameters—Aal1 CES
    863
    
    INTMSK Mask Bits
    863
    
    Channel Mode Register (CHAMR)—CES Mode
    864
    
    Channel-Specific SS7 Parameters
    865
    
    Extended Channel Mode Register (ECHAMR)—SS7 Mode
    869
    
    Extended Channel Mode Register (ECHAMR)
    870
    
    Signal Unit Error Monitor (SUERM)—SS7 Mode
    871
    
    SUERM in Japanese SS7
    871
    
    SS7 Configuration Register—Ss7 Mode
    872
    
    AERM Implementation
    873
    
    AERM in Japanese SS7
    873
    
    Comparison Mask
    874
    
    Comparison State Machine
    874
    
    Disabling SUERM
    874
    
    Mask1 Format
    874
    
    Mask2 Format
    874
    
    SU Filtering—Ss7 Mode
    874
    
    Filtering Limitations
    875
    
    Resetting the SU Filtering Mechanism
    875
    
    Octet Counting Mode—Ss7 Mode
    876
  - Channel Extra Parameters
    876
  - Superchannels
    877
    
    Super Channel Table Entry
    877
    
    Superchannel Table
    877
    
    Superchannelling Programming Examples
    878
    
    Superchannels and Receiving
    878
    
    Transparent Slot Synchronization
    878
    
    Transmitter Super Channel Example
    879
    
    Receiver Super Channel with Slot Synchronization Example
    880
  - MCC Configuration Registers (Mccfx)
    881
    
    Receiver Super Channel Without Slot Synchronization Example
    881
    
    SI MCC Configuration Register (MCCF)
    881
  - MCC Commands
    882
  - MCC Exceptions
    883
    
    Interrupt Circular Table
    884
    
    MCC Event Register (Mcce)/Mask Register (MCCM)
    885
    
    Interrupt Circular Table Entry
    886
    
    Global Transmitter Underrun (GUN)
    888
    
    Synchronization Pulse
    888
    
    TDM Clock
    888
    
    CPM Bandwidth
    889
    
    MCC Initialization
    889
    
    SIRAM Programming
    889
    
    Bus Latency
    890
    
    CPM Priority
    890
    
    Recovery from GUN Errors
    890
    
    Global Overrun (GOV)
    891
  - MCC Buffer Descriptors
    891
    
    MCC Receive Buffer Descriptor (Rxbd)
    891
    
    Receive Buffer Descriptor (Rxbd)
    891
    
    Transmit Buffer Descriptor (Txbd)
    893
    
    MCC Transmit Buffer Descriptor (Txbd)
    894
  - MCC Initialization and Start/Stop Sequence
    895
    
    Stopping and Restarting a Single-Channel
    896
    
    Stopping and Restarting a Superchannel
    897
  - MCC Latency and Performance
    897
    
    Overview
    899
- Chapter 29
  
  901
  - General FCC Mode Registers (Gfmrx)
    901
    
    FCC Block Diagram
    901
    
    General FCC Mode Register (GFMR)
    902
  - FCC Protocol-Specific Mode Registers (Fpsmrx)
    905
  - FCC Data Synchronization Registers (Fdsrx)
    906
  - FCC Transmit-On-Demand Registers (Ftodrx)
    906
  - FCC Buffer Descriptors
    907
    
    FCC Transmit-On-Demand Register (FTODR)
    907
    
    Buffer Descriptor Format
    908
    
    FCC Memory Structure
    908
  - FCC Parameter RAM
    909
    
    FCC Function Code Registers (Fcrx)
    911
    
    Function Code Register (Fcrx)
    911
  - Interrupts from the Fccs
    912
    
    FCC Event Registers (Fccex)
    912
    
    FCC Mask Registers (Fccmx)
    913
  - FCC Initialization
    913
  - FCC Interrupt Handling
    914
    
    FCC Transmit Errors
    914
    
    Re-Initialization Procedure
    914
    
    Adjusting Transmitter BD Handling
    915
    
    Recovery Sequence
    915
  - FCC Timing Control
    915
    
    Output Delay from CTS Asserted
    916
    
    Output Delay from RTS Asserted
    916
    
    CTS Lost
    917
  - Disabling the Fccs On-The-Fly
    918
    
    Using CD to Control Reception
    918
    
    FCC Receiver Full Sequence
    919
    
    FCC Receiver Shortcut Sequence
    919
    
    FCC Transmitter Full Sequence
    919
    
    FCC Transmitter Shortcut Sequence
    919
    
    Switching Protocols
    920
  - Saving Power
    920
    
    Features
    921
  - ATM Controller Overview
    924
- Chapter 30
  
  925
  - AAL5 Transmitter Overview
    925
  - AAL1 Transmitter Overview
    925
  - Transmitter Overview
    925
  - AAL1 CES Transmitter Overview
    926
    
    AAL0 Transmitter Overview
    926
    
    AAL2 Transmitter Overview
    926
    
    Receiver Overview
    926
    
    Transmit External Rate and Internal Rate Modes
    926
    
    AAL1 Receiver Overview
    927
    
    AAL5 Receiver Overview
    927
  - AAL1 CES Receiver Overview
    928
    
    AAL0 Receiver Overview
    928
    
    AAL2 Receiver Overview
    928
    
    ABR Flow Control
    928
    
    APC Modes and ATM Service Types
    928
    
    ATM Pace Control (APC) Unit
    928
    
    Performance Monitoring
    928
    
    APC Scheduling Table Mechanism
    929
    
    APC Unit Scheduling Mechanism
    929
    
    Determining the Cells Per Slot (CPS) in a Scheduling Table
    930
    
    Determining the Number of Slots in a Scheduling Table
    930
    
    Determining the Scheduling Table Size
    930
    
    ATM Traffic Type
    931
    
    Determining the PCR Traffic Type Parameters
    931
    
    Determining the Time-Slot Scheduling Rate of a Channel
    931
    
    Peak Cell Rate Traffic Type
    931
    
    Example for Using VBR Traffic Parameters
    932
    
    Peak and Sustain Traffic Type (VBR)
    932
    
    VBR Pacing Using the GCRA (Leaky Bucket Algorithm)
    932
    
    Determining the Priority of an ATM Channel
    933
    
    Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2
    933
    
    Peak and Minimum Cell Rate Traffic Type (UBR+)
    933
  - VCI/VPI Address Lookup Mechanism
    933
    
    External CAM Data Input Fields
    934
    
    External CAM Lookup
    934
    
    External CAM Output Fields
    934
    
    Address Compression
    935
    
    Address Compression Mechanism
    935
    
    General VCOFFSET Formula for Contiguous Vclts
    936
    
    VP-Level Address Compression Table (VPLT)
    936
    
    VC-Level Address Compression Tables (Vclts)
    937
    
    VP Pointer Address Compression
    937
    
    Misinserted Cells
    938
    
    Receive Raw Cell Queue
    938
    
    VC Pointer Address Compression
    938
  - Available Bit Rate (ABR) Flow Control
    939
    
    ATM Address Recognition Flowchart
    939
    
    ABR Flow Control Source End-System Behavior
    940
    
    Powerquicc II's ABR Basic Model
    940
    
    The ABR Model
    940
    
    ABR Flow Control Destination End-System Behavior
    941
    
    ABR Flowcharts
    941
    
    ABR Transmit Flow
    942
    
    ABR Transmit Flow (Continued)
    943
    
    ABR Transmit Flow (Continued)
    944
    
    ABR Receive Flow
    945
    
    RM Cell Structure
    945
    
    Rate Format for RM Cells
    946
    
    Rate Formula for RM Cells
    946
    
    RM Cell Rate Representation
    946
    
    ABR Flow Control Setup
    947
  - OAM Support
    947
    
    ATM-Layer OAM Definitions
    947
    
    Receiving OAM F4 or F5 Cells
    948
    
    Transmitting OAM F4 or F5 Cells
    948
    
    Virtual Channel (F5) Flow Mechanism
    948
    
    Performance Monitoring
    949
    
    Performance Monitoring Cell Structure (Fmcs and Brcs)
    949
    
    PM Block Monitoring
    950
    
    Running a Performance Block Test
    950
    
    FMC, BRC Insertion
    951
    
    PM Block Generation
    951
    
    BRC Performance Calculations
    952
  - User-Defined Cells (UDC)
    952
    
    Format of User-Defined Cells
    952
    
    UDC Extended Address Mode (UEAD)
    952
    
    ATM Layer Statistics
    953
    
    ATM-To-TDM Interworking
    953
    
    Automatic Data Forwarding
    953
    
    External CAM Address in UDC Extended Address Mode
    953
    
    ATM-To-TDM Interworking
    954
    
    Using Interrupts in Automatic Data Forwarding
    954
    
    CAS Support
    955
    
    Clock Synchronization (SRTS and Adaptive Fifos)
    955
    
    Mapping TDM Time Slots to Vcs
    955
    
    Timing Issues
    955
    
    ATM Memory Structure
    956
    
    ATM-To-ATM Data Forwarding
    956
    
    Parameter RAM
    956
    
    Trunk Condition
    956
    
    Determining UEAD_OFFSET (UEAD Mode Only)
    959
    
    VCI Filtering (VCIF)
    959
    
    VCI Filtering Enable Bits
    959
    
    Global Mode Entry (GMODE)
    960
    
    ATM Channel Code
    961
    
    Connection Tables (RCT, TCT, and TCTE)
    961
    
    Example of a 1024-Entry Receive Connection Table
    962
    
    Receive Connection Table (RCT)
    962
    
    Receive Connection Table (RCT) Entry
    963
    
    AAL5 Protocol-Specific RCT
    965
    
    AAL5 Protocol-Specific RCT
    966
    
    AAL5-ABR Protocol-Specific RCT
    966
    
    AAL1 Protocol-Specific RCT
    967
    
    AAL5-ABR Protocol-Specific RCT
    967
    
    AAL0 Protocol-Specific RCT
    969
    
    AAL1 CES Protocol-Specific RCT
    970
    
    AAL2 Protocol-Specific RCT
    970
    
    Transmit Connection Table (TCT)
    970
    
    Transmit Connection Table (TCT) Entry
    970
    
    AAL1 Protocol-Specific TCT
    975
    
    AAL5 Protocol-Specific TCT
    975
    
    AAL1 Protocol-Specific TCT
    976
    
    AAL0 Protocol-Specific TCT
    977
    
    AAL1 CES Protocol-Specific TCT
    977
    
    AAL2 Protocol-Specific TCT
    977
    
    VBR Protocol-Specific TCTE
    977
    
    Transmit Connection Table Extension (TCTE)—VBR Protocol-Specific
    978
    
    UBR+ Protocol-Specific TCTE
    978
    
    ABR Protocol-Specific TCTE
    979
    
    UBR+ Protocol-Specific TCTE
    979
    
    ABR Protocol-Specific TCTE
    980
    
    OAM Performance Monitoring Tables
    982
    
    APC Data Structure
    983
    
    APC Parameter Tables
    984
    
    ATM Pace Control Data Structure
    984
    
    APC Priority Table
    985
    
    APC Scheduling Tables
    985
    
    The APC Scheduling Table Structure
    985
    
    ATM Controller Buffer Descriptors (Bds)
    986
    
    Control Slot
    986
    
    Transmit Buffer Operation
    986
    
    Receive Buffer Operation
    987
    
    Static Buffer Allocation
    987
    
    Transmit Buffers and BD Table Example
    987
    
    Global Buffer Allocation
    988
    
    Receive Static Buffer Allocation Example
    988
    
    Free Buffer Pool Structure
    989
    
    Free Buffer Pools
    989
    
    Receive Global Buffer Allocation Example
    989
    
    Free Buffer Pool Entry
    990
    
    Free Buffer Pool Parameter Tables
    990
  - ATM Controller Buffers
    991
    
    AAL5 Rxbd
    991
    
    AAL1 Rxbd
    993
    
    AAL0 Rxbd
    994
    
    AAL1 CES Rxbd
    995
    
    AAL2 Rxbd
    995
    
    AAL5 Txbds
    996
    
    AAL5, AAL1 CES User-Defined Cell—Rxbd Extension
    996
    
    AAL1 Txbds
    997
    
    AAL0 Txbds
    998
    
    AAL1 Txbd
    998
    
    AAL0 Txbds
    999
    
    AAL1 CES Txbds
    999
    
    AAL1 Sequence Number (SN) Protection Table
    1000
    
    AAL2 Txbds
    1000
    
    AAL5, AAL1 User-Defined Cell—Txbd Extension
    1000
    
    UNI Statistics Table
    1001
  - ATM Exceptions
    1001
    
    Interrupt Queues
    1001
    
    Interrupt Queue Entry
    1002
    
    Interrupt Queue Structure
    1002
    
    Interrupt Queue Parameter Tables
    1003
  - The UTOPIA Interface
    1004
    
    UTOPIA Interface Master Mode
    1004
    
    UTOPIA Master Mode Signals
    1004
    
    UTOPIA Master Multiple PHY Operation
    1005
    
    UTOPIA Interface Slave Mode
    1006
    
    UTOPIA Slave Mode Signals
    1006
    
    UTOPIA Clocking Modes
    1007
    
    UTOPIA Loop-Back Modes
    1007
    
    UTOPIA Slave Multiple PHY Operation
    1007
  - ATM Registers
    1007
    
    FCC ATM Mode Register (FPSMR)
    1008
    
    FCC Protocol-Specific Mode Register (FPSMR)
    1008
    
    General FCC Mode Register (GFMR)
    1008
    
    ATM Event Register (Fcce)/Mask Register (FCCM)
    1010
    
    ATM Event Register (FCCE)/FCC Mask Register (FCCM)
    1011
    
    FCC Transmit Internal Rate Registers (Ftirrx) (FCC1 and FCC2 Only)
    1011
    
    FCC Transmit Internal Rate Clocking
    1012
    
    FCC Transmit Internal Rate Registers (Ftirrx)
    1012
  - ATM Transmit Command
    1013
    
    COMM_INFO Field
    1013
  - SRTS Generation and Clock Recovery Using External Logic
    1014
    
    AAL1 CES SRTS Generation Using External Logic
    1014
  - Configuring the ATM Controller for Maximum CPM Performance
    1015
    
    AAL1 CES SRTS Clock Recovery Using External Logic
    1015
    
    Using Transmit Internal Rate Mode
    1015
    
    APC Configuration
    1016
    
    Buffer Configuration
    1016
    
    Features
    1017
- Chapter 32
  
  925
- Chapter 31
  
  1019
  - AAL1 CES Transmitter Overview
    1019
  - AAL1 SDT Cells Type
    1019
  - AAL1 Transmit Cell Format
    1019
  - Data Path
    1019
  - Signaling Path
    1019
  - AAL1 CES Receiver Overview
    1020
  - AAL1 Framing Formats
    1020
  - AAL1 CES Receiver Data Flow
    1022
    
    ATM-To-TDM
    1023
    
    ATM-To-TDM Interworking
    1023
    
    TDM-To-ATM
    1023
  - Automatic Data Forwarding
    1022
  - Interworking Functions
    1022
  - TDM-To-ATM Interworking
    1024
  - Timing Issues
    1024
  - Clock Synchronization (SRTS, Adaptive FIFO)
    1025
  - Mapping TDM Time Slots to Vcs
    1025
  - Channel Associated Signaling (CAS) Support
    1026
  - Mapping cas Data on a Serial Interface
    1026
  - Trunk Condition
    1026
  - Internal cas Block Formats
    1027
    
    CAS Routing Table
    1028
  - Mapping VC Signaling to cas Blocks
    1027
  - AAL1 CES cas Routing Table (CRT)
    1028
  - AAL1 CES cas Routing Table Entry
    1028
    
    TDM-To-ATM cas Support
    1029
  - Mapping cas Entry
    1028
  - CAS Flow TDM-To-ATM
    1029
    
    ATM-To-TDM cas Support
    1030
    
    CAS Mapping Using the Core (Optional)
    1030
  - CAS Flow ATM-To-TDM
    1030
    
    CAS Updates Using the Core (Optional)
    1031
  - ATM-To-TDM Adaptive Slip Control
    1031
    
    CES Adaptive Threshold Tables
    1032
    
    Data Structure for ATM-To-TDM Adaptive Slip Control
    1032
    
    CES Adaptive Threshold Table
    1033
    
    Pre-Underrun Sequence
    1034
    
    Pre-Overrun Sequence
    1035
  - Step-SN Algorithm
    1036
    
    Recoverable Sync Fail Sequence Options
    1036
    
    The Three States of the Algorithm
    1036
    
    Pointer Verification Mechanism
    1037
    
    Step-SN-Algorithm
    1037
  - AAL-1 Memory Structure
    1038
    
    AAL1 CES Parameter RAM
    1038
    
    Pointer Verification Mechanism
    1038
    
    Receive and Transmit Connection Tables (RCT, TCT)
    1041
    
    Receive Connection Table (RCT)
    1042
    
    Receive Connection Table (RCT) Entry
    1042
    
    AAL1 CES Protocol-Specific RCT
    1044
    
    Transmit Connection Table (TCT)
    1047
    
    Transmit Connection Table (TCT) Entry
    1047
    
    AAL1 CES Protocol-Specific TCT
    1050
    
    Outgoing cas Status Register (OCASSR)
    1051
    
    Buffer Descriptors
    1052
    
    Transmit Buffer Operation
    1052
    
    Receive Buffer Operation
    1053
    
    Transmit Buffers and BD Table Example
    1053
    
    AAL1 CES Rxbd
    1054
    
    ATM Controller Buffers
    1054
    
    Receive Buffers and BD Table Example
    1054
    
    AAL1 CES Rxbd
    1055
    
    AAL1 CES Txbd
    1056
    
    AAL1 CES Txbds
    1056
  - AAL1 CES Exceptions
    1057
    
    AAL1 CES Interrupt Queue Entry
    1057
    
    AAL1 Sequence Number (SN) Protection Table
    1058
  - Internal AAL1 CES Statistics Tables
    1059
    
    AAL1 Sequence Number (SN) Protection Table
    1059
  - Application Considerations
    1060
    
    TDM-To-ATM Timing Issue
    1061
    
    AAL2 Data Units
    1063
    
    Introduction
    1063
    
    AAL2 Sublayer Structure
    1064
    
    AAL2 Switching Example
    1065
    
    Features
    1065
  - CES-Specific Additions to the MCC
    1060
  - External AAL1 CES Statistics Tables
    1060
  - AAL2 Transmitter
    1067
    
    Transmit Priority Mechanism
    1067
    
    Transmitter Overview
    1067
    
    Fixed Priority
    1068
    
    Round Robin Priority
    1068
    
    Fixed Priority Mode
    1069
    
    Partial Fill Mode (Pfm)
    1069
    
    AAL2 Tx Data Structures
    1070
    
    No STF Mode
    1070
    
    AAL2 Protocol-Specific TCT
    1071
    
    AAL2 Protocol-Specific Transmit Connection Table (TCT)
    1071
    
    CPS Tx Queue Descriptor
    1075
    
    CPS Tx Queue Descriptor (Txqd)
    1076
    
    Buffer Structure Example for CPS Packets
    1077
    
    CPS Buffer Structure
    1077
    
    CPS Txbd
    1078
    
    CPS Packet Header Format
    1079
    
    SSSAR Tx Queue Descriptor
    1079
    
    SSSAR Transmit Buffer Descriptor
    1081
    
    SSSAR Txbd
    1081
  - AAL2 Receiver
    1082
    
    Receiver Overview
    1082
    
    Mapping of PHY | VP | VC | CID
    1083
    
    AAL2 Switching
    1084
    
    CID Mapping Process
    1084
    
    AAL2 RX Data Structures
    1085
    
    AAL2 Switching
    1085
    
    AAL2 Protocol-Specific RCT
    1086
    
    AAL2 Protocol-Specific Receive Connection Table (RCT)
    1086
    
    CID Mapping Tables and Rxqds
    1089
    
    CPS Rx Queue Descriptors
    1089
    
    CPS Receive Buffer Descriptor
    1090
    
    CPS Switch Rx Queue Descriptor
    1091
    
    CPS Switch Rx Queue Descriptor
    1092
    
    Switch Receive/Transmit Buffer Descriptor
    1092
    
    SSSAR Rx Queue Descriptor
    1093
    
    SSSAR Rx Queue Descriptor
    1094
    
    SSSAR Receive Buffer Descriptor
    1095
  - AAL2 Parameter RAM
    1097
    
    User-Defined Cells in AAL2
    1100
  - AAL2 Exceptions
    1100
    
    UDC Header Table
    1100
    
    AAL2 Interrupt Queue Entry CID = 0
    1101
    
    Features
    1103
    
    IMA Versions Supported
    1105
    
    PHY-Layer Devices Supported
    1105
    
    Powerquicc II Versions Supported
    1105
    
    References
    1105
    
    Additional Impact on Powerquicc II Features
    1106
    
    ATM Features Not Supported
    1106
- Chapter 33
  
  1105
  - IMA Protocol Overview
    1106
    
    Introduction
    1106
    
    Basic Concept of IMA
    1107
    
    IMA Frame Overview
    1107
    
    Illustration of IMA Frames
    1108
    
    IMA Microcode Overview
    1108
    
    IMA Control Cells
    1109
    
    Overview of IMA Cells
    1109
    
    IMA Filler Cells
    1112
  - IMA Microcode Architecture
    1112
    
    IMA Frame and ICP Cell Formats
    1112
    
    IMA Function Partitioning
    1112
    
    Plane Management Functions Performed by Microcode
    1113
    
    Transmit Architecture
    1113
    
    User Plane Functions Performed by Microcode
    1113
    
    IMA Transmit Task Interaction
    1114
    
    TRL Operation
    1114
    
    Non-TRL Operation
    1115
    
    TRL Service Latency
    1115
    
    Transmit Queue Behavior: Link Clock Rate same as TRL
    1116
    
    Transmit Queue Normal Operating State
    1116
    
    Transmit Queue Operation Examples (ITC Mode)
    1116
    
    Transmit Queue Behavior: Link Clock Rate Slower than TRL
    1117
    
    Differences in CTC Operation
    1118
    
    Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence
    1118
    
    Cell Reception Task
    1119
    
    IMA Receive Task Interaction
    1119
    
    Receive Architecture
    1119
    
    IMA Microcode: Receive Process
    1123
    
    Cell Processing Activation Function
    1124
    
    On-Demand Cell Processing
    1124
    
    IDCR-Regulated Cell Processing
    1125
    
    Cell Processing Task
    1126
  - IMA Programming Model
    1126
    
    Data Structure Organization
    1126
    
    IMA Root Table Data Structures
    1127
    
    FCC Parameters
    1128
    
    FCC Registers
    1128
    
    Fpsmrx
    1128
    
    Ftirrx
    1128
    
    Gmode
    1128
    
    IMA FCC Programming
    1128
    
    IMA-Specific FCC Parameters
    1128
    
    TCELL_TMP_BASE and RCELL_TMP_BASE
    1128
    
    IMA Root Table
    1129
    
    IMA Control (IMACNTL)
    1131
    
    IMA Group Tables
    1131
    
    IMA Group Transmit Table Entry
    1132
    
    IMA Group Transmit Control (IGTCNTL)
    1133
    
    IMA Group Transmit State (IGTSTATE)
    1133
    
    IMA Group Transmit State (IGTSTATE)
    1134
    
    Transmit Group Order Table
    1134
    
    Transmit Group Order Table Entry
    1134
    
    ICP Cell Templates
    1135
    
    IMA Group Receive Table Entry
    1138
    
    IMA Group Receive Control (IGRCNTL)
    1140
    
    IMA Group Receive State (IGRSTATE)
    1141
    
    IMA Receive Group Frame Size
    1141
    
    IMA Receive Group Frame Size (IGRSTATE)
    1142
    
    Receive Group Order Table Entry
    1142
    
    Receive Group Order Tables
    1142
    
    IMA Link Tables
    1143
    
    IMA Link Transmit Table Entry
    1143
    
    IMA Link Transmit Control (ILTCNTL)
    1144
    
    IMA Link Transmit State (ILTSTATE)
    1145
    
    IMA Transmit Interrupt Status (ITINTSTAT)
    1145
    
    IMA Link Receive Table Entry
    1146
    
    IMA Link Receive Control (ILRCNTL)
    1148
    
    IMA Link Receive State (ILRSTATE)
    1149
    
    IMA Link Receive Statistics Table
    1150
    
    IMA Transmit Queue
    1150
    
    Structures in External Memory
    1150
    
    Transmit Queues
    1150
    
    Cell Buffer in Delay Compensation Buffer
    1151
    
    Delay Compensation Buffers (DCB)
    1151
    
    IMA Delay Compensation Buffer
    1151
    
    IMA Exceptions
    1151
    
    IMA Interrupt Queue Entry
    1152
    
    ICP Cell Reception Exceptions
    1153
    
    IDCR FCC Parameter Shadow
    1154
    
    IDCR Master Clock
    1154
    
    IDCR Timer Programming
    1154
    
    Powerquicc II Features Unavailable if IDCR Is Used
    1154
    
    On-The-Fly Changes of FCC Parameters
    1155
    
    Programming the FCC Parameter Shadow
    1155
    
    IDCR Root Parameters
    1156
    
    IDCR Table Entry
    1156
    
    Idcr_Init Command
    1156
    
    IDCR Counter Algorithm
    1157
    
    IDCR Events
    1157
    
    IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR)
    1157
    
    APC Programming for IMA
    1158
    
    Programming for ABR
    1159
    
    Programming for CBR, UBR, VBR, and UBR+
    1159
    
    Changing IMA Version
    1160
  - IMA Software Interface and Requirements
    1160
    
    COMM_INFO Field
    1160
    
    Software Model
    1160
    
    IMA Microcode/Software Interaction
    1161
    
    Initialization Procedure
    1161
    
    Software Responsibilities
    1161
    
    System Definition
    1161
    
    General Operation
    1162
    
    Receive Group State Machine Control
    1162
    
    Receive Link State Machine Control
    1162
    
    Transmit Link State Machine Control
    1162
    
    Failure Alarms
    1163
    
    Group Symmetry Control
    1163
    
    ICP End-To-End Channel Transmission
    1163
    
    Link Addition and Slow Recovery (LASR) Procedure
    1163
    
    Transmit Group State Machine Control
    1163
    
    IMA Software Procedures
    1164
    
    Performance Parameter Measurement and Reporting
    1164
    
    Receive Link Start-Up Procedure
    1164
    
    SNMP Mibs
    1164
    
    Test Pattern Control
    1164
    
    Transmit ICP Cell Signalling
    1164
    
    Group Start-Up Procedure
    1165
    
    As Initiator (Tx)
    1166
    
    As Responder (Rx)
    1167
    
    Link Addition Procedure
    1167
    
    Near-End Versus Far-End
    1167
    
    Rx Steps
    1167
    
    TX Parameters
    1168
    
    Link Removal Procedure
    1169
    
    Rx Steps
    1169
    
    Link Receive Deactivation Procedure
    1170
    
    TX Parameters
    1170
    
    Link Receive Reactivation Procedure
    1171
    
    TRL On-The-Fly Change Procedure
    1171
    
    Receive Event Response Procedures
    1172
    
    Transmit Event Response Procedures
    1172
    
    As Initiator (Ne)
    1174
    
    As Responder (Fe)
    1174
    
    Test Pattern Procedure
    1174
    
    IDCR Operation
    1175
    
    IDCR Start-Up
    1175
    
    Activating a Group in IDCR Mode
    1176
    
    End-To-End Channel Signalling Procedure
    1176
    
    Transmit
    1176
    
    Receive
    1177
    
    Features
    1179
    
    Serial ATM Using FCC2 and TC Blocks (Single Channel)
    1179
  - Functionality
    1181
    
    Receive ATM Cell Functions
    1182
    
    TC Layer Block Diagram
    1182
    
    TC Cell Delineation State Machine
    1183
- Chapter 34 Receive ATM 2-Cell FIFO
  
  1184
  - HEC: Receiver Modes of Operation
    1184
  - Transmit ATM Cell Functions
    1184
    
    Transmit ATM 2-Cell FIFO
    1184
  - Receive UTOPIA Interface
    1185
  - TC Layer Programming Mode
    1185
    
    TC Layer Mode Register [1–8] (Tcmodex)
    1185
    
    TC Layer Registers
    1185
    
    TC Layer Mode Register (Tcmodex)
    1186
    
    Cell Delineation State Machine Register [1–8] (Cdsmrx)
    1187
    
    TC Layer Event Register [1–8] (Tcerx)
    1188
    
    TC Layer General Event Register (TCGER)
    1189
    
    TC Layer General Registers
    1189
    
    TC Layer General Status Register (TCGSR)
    1189
    
    TC Layer Mask Register (Tcmrx)
    1189
    
    Corrected Cell Counter [1–8] (Tc_Cccx)
    1190
    
    Errored Cell Counter [1–8] (Tc_Eccx)
    1190
    
    Received Cell Counter [1–8] (Tc_Rccx)
    1190
    
    TC Layer Cell Counters
    1190
    
    TC Layer General Status Register (TCGSR)
    1190
    
    Transmitted Cell Counter [1–8] (Tc_Tccx)
    1190
    
    Transmitted IDLE Cell Counter [1–8] (Tc_Iccx)
    1190
    
    Filtered Cell Counter [1–8] (Tc_Fccx)
    1191
    
    Programming and Operating the TC Layer
    1191
    
    Programming FCC2
    1191
    
    Receive
    1191
    
    Transmit
    1191
    
    TC Operation in FCC External Rate Mode
    1192
  - Transmit UTOPIA Interface
    1185
    
    Signals
    1185
  - Implementation Example
    1193
    
    TC Operation in FCC Internal Rate Mode (Sub Rate Mode)
    1193
    
    Example of Serial ATM Application
    1194
    
    Operating the TC Layer at Higher Frequencies
    1194
    
    Programming a T1 Application
    1194
    
    Step 1
    1195
    
    Step 2
    1195
    
    Step 3
    1195
    
    Step 4
    1195
    
    Step 5
    1195
    
    Step 6
    1196
    
    Step 7
    1196
    
    Ethernet Frame Structure
    1197
- Chapter 35
  
  1198
  - Fast Ethernet on the Powerquicc II
    1198
    
    Ethernet Block Diagram
    1198
    
    Features
    1198
  - Connecting the Powerquicc II to Fast Ethernet
    1200
    
    Connecting the Powerquicc II to Ethernet
    1200
  - Ethernet Channel Frame Transmission
    1201
  - Ethernet Channel Frame Reception
    1202
  - CAM Interface
    1203
  - Flow Control
    1203
  - Ethernet Parameter RAM
    1204
  - Ethernet Command Set
    1207
    
    Programming Model
    1207
  - RMON Support
    1209
  - Ethernet Address Recognition
    1210
    
    Ethernet Address Recognition Flowchart
    1212
    
    Hash Table Algorithm
    1212
    
    Handling Collisions
    1213
    
    Internal and External Loopback
    1213
    
    Interpacket Gap Time
    1213
  - Ethernet Error-Handling Procedure
    1213
  - Fast Ethernet Registers
    1214
    
    FCC Ethernet Mode Register (FPSMR)
    1214
    
    FCC Ethernet Mode Registers (FPSMR)
    1215
    
    Ethernet Event Register (Fcce)/Mask Register (FCCM)
    1216
  - Ethernet Rxbds
    1218
    
    Ethernet Interrupt Events Example
    1218
    
    Fast Ethernet Receive Buffer (Rxbd)
    1219
  - Ethernet Txbds
    1221
    
    Ethernet Receiving Using Rxbds
    1221
    
    Fast Ethernet Transmit Buffer (Txbd)
    1222
- Chapter 36
  
  1225
  - Key Features
    1225
  - HDLC Channel Frame Transmission Processing
    1226
    
    HDLC Framing Structure
    1226
  - HDLC Channel Frame Reception Processing
    1227
  - HDLC Parameter RAM
    1227
    
    HDLC Address Recognition Example
    1229
    
    HDLC Command Set
    1229
    
    Programming Model
    1229
    
    HDLC Error Handling
    1230
    
    HDLC Mode Register (FPSMR)
    1231
    
    HDLC Mode Register (FPSMR)
    1232
  - HDLC Receive Buffer Descriptor (Rxbd)
    1233
    
    FCC HDLC Receiving Using Rxbds
    1234
    
    FCC HDLC Receive Buffer Descriptor (Rxbd)
    1235
  - HDLC Transmit Buffer Descriptor (Txbd)
    1236
    
    FCC HDLC Transmit Buffer Descriptor (Txbd)
    1236
    
    HDLC Event Register (Fcce)/Mask Register (FCCM)
    1238
    
    FCC Status Register (FCCS)
    1240
    
    HDLC Interrupt Event Example
    1240
    
    Features
    1243
- Chapter 37
  
  1244
  - Transparent Channel Operation
    1244
    
    Achieving Synchronization in Transparent Mode
    1244
    
    In-Line Synchronization Pattern
    1244
    
    External Synchronization Signals
    1245
    
    Transparent Synchronization Example
    1245
    
    Sending Transparent Frames between Powerquicc Iis
    1246
    
    Features
    1247
    
    SPI Block Diagram
    1247
- Chapter 38
  
  1248
  - SPI Clocking and Signal Functions
    1248
  - Configuring the SPI Controller
    1249
    
    Single-Master/Multi-Slave Configuration
    1249
    
    The SPI as a Master Device
    1249
    
    The SPI as a Slave Device
    1250
    
    The SPI in Multimaster Operation
    1250
    
    Multimaster Configuration
    1251
  - Programming the SPI Registers
    1252
    
    SPI Mode Register (SPMODE)
    1252
    
    SPMODE—SPI Mode Register
    1252
    
    SPI Transfer Format with SPMODE[CP] = 0
    1253
    
    SPI Examples with Different SPMODE[LEN] Values
    1254
    
    SPI Transfer Format with SPMODE[CP] = 1
    1254
    
    SPI Event/Mask Registers (SPIE/SPIM)
    1255
    
    SPIE/SPIM—SPI Event/Mask Registers
    1255
    
    SPI Command Register (SPCOM)
    1256
  - SPI Parameter RAM
    1256
    
    SPCOM—SPI Command Register
    1256
    
    Receive/Transmit Function Code Registers (RFCR/TFCR)
    1258
  - SPI Commands
    1258
    
    Rfcr/Tfcr—Function Code Registers
    1258
  - The SPI Buffer Descriptor (BD) Table
    1259
    
    SPI Buffer Descriptors (Bds)
    1259
    
    SPI Memory Structure
    1259
    
    SPI Receive BD (Rxbd)
    1260
    
    SPI Rxbd
    1260
    
    SPI Transmit BD (Txbd)
    1261
    
    SPI Txbd
    1261
  - SPI Master Programming Example
    1262
  - SPI Slave Programming Example
    1263
  - Handling Interrupts in the SPI
    1264
    
    I 2 C Master Read (Slave Write)
    1268
    
    I 2 C Multi-Master Considerations
    1269
    
    I 2 C Address Register (I2ADD)
    1270
    
    I 2 C Baud Rate Generator Register (I2BRG)
    1271
    
    I 2 C Buffer Descriptors (Bds)
    1276
    
    I 2 C Receive Buffer Descriptor (Rxbd)
    1276
    
    I2C Rxbd
    1276
    
    I2C Txbd
    1276
- Chapter 40 Port Registers
  
  1279
  - Features
    1279
  - Port Open-Drain Registers (PODRA–PODRD)
    1279
  - Port Data Registers (PDATA–PDATD)
    1280
  - Port Open-Drain Registers (PODRA–PODRD)
    1280
  - Port Data Direction Registers (PDIRA–PDIRD)
    1281
  - Port Data Registers (PDATA–PDATD)
    1281
  - Port Pin Assignment Register (PPARA–PPARD)
    1282
  - Port Special Options Registers A–D (PSORA–PSORD)
    1282
  - Port Block Diagram
    1283
    
    Special Options Registers (PSORA–POSRD)
    1283
  - Port Pins Functions
    1284
    
    Port Functional Operation
    1284
    
    Dedicated Pins
    1285
    
    General Purpose I/O Pins
    1285
  - Ports Tables
    1285
    
    Primary and Secondary Option Programming
    1286
  - Interrupts from Port C
    1297
    
    A.1 Powerpc Registers—User Registers
    1299
    
    A.2 Powerpc Registers—Supervisor Registers
    1299
    
    A.3 MPC8260-Specific Sprs
    1301
    
    B.1 Document Errata
    1303
    
    Start_Idma Command
    1309
    
    Utopia Interface
    1312
    
    Trl Service Latency
    1313
Table of Contents

1330
- Set Timer Command
  1335
Table of Contents

1340
- Message Unit (I2O)
  1344
  - I2O Registers
    1347
  - I2O Unit
    1348
- Message Unit (I2O) Registers
  1344

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Freescale Semiconductor MPC8250 Family Reference Manual (1360 pages)

Table of Contents

Table of Contents

Chapter 3 System Interface Unit (SIU)

Chapter 1 Communications Processor Module (CPM)

Chapter 2 G2 Processor Core Features

Chapter 5

Chapter 6

Chapter 7 Address Bus Arbitration Signals

Chapter 8

Chapter 9

Chapter 10

Chapter 11 Memory Controller

Chapter 12

Chapter 13 Powerquicc II Restrictions

Chapter 14 Communications Processor Module

Chapter 15

Chapter 16

Chapter 17

Chapter 18

Chapter 19

Chapter 20 The General SCC Mode Registers (GSMR1–GSMR4)

Chapter 21

Chapter 22

Chapter 23

Chapter 24

Chapter 25

Chapter 26 SCC Appletalk Mode

Chapter 27 Common SMC Settings and Configurations

Chapter 28 MCC Data Structure Organization

Chapter 29

Chapter 30

Chapter 32

Chapter 31

Chapter 33

Chapter 34 Receive ATM 2-Cell FIFO

Chapter 35

Chapter 36

Chapter 37

Chapter 38

Chapter 40 Port Registers

Table of Contents

Table of Contents

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