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f(X
)
IN
,
C PU
B I U
Interrupt request
used to terminate
Stop mode
(Interrupt request bit)
"FFF
Value of watchdog timer
"7FF
C PU
Internal peripheral devices
Fig. 10.2.1 Stop mode terminating sequence by interrupt request occurrence
10.2.2 Termination by hardware reset
Supply "L" level to the RESET pin by using the external circuit until the oscillation of the oscillator is
stabilized.
The CPU and the SFR area are initialized in the same way as the system reset. However, the internal RAM
area retains the same contents as that before executing the STP instruction. The termination sequence is
the same as the internal processing sequence which is performed after a reset.
To determine whether a hardware reset was performed to terminate Stop mode or a system reset was
performed, use software after a reset.
Refer to "Chapter 13. RESET" for details about a reset.
Stop mode
"1"
"0"
"
16
"
16
Operating
Stopped
Stopped
Operating
STP instruction
is executed
______
7751 Group User's Manual
10.2 Operation description
. . . . . . .
Wf
/Wf
2048 counts
32
64
Stopped
Operating
Interrupt request used to
terminate Stop mode
occurs.
Oscillation starts.(When
an external clock is input
from the X
pin, clock
IN
input starts.)
Watchdog timer starts
counting.
STOP MODE
Operating
Operating
Watchdog timer's MSB = "0"
(However, watchdog timer interrupt
request does not occur.)
Supply of
,
starts.
CPU
BIU
Interrupt request which has been
used to terminate Stop mode is
accepted.
10–5
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