Interrupt Response Time; Usage Notes - Hitachi H8/3035 Series Hardware Manual

5.4.3 Interrupt Response Time

Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until
the first instruction of the interrupt service routine is executed.
Table 5-5 Interrupt Response Time
No. Item
1 Interrupt priority decision
2 Maximum number of states
until end of current instruction
3 Saving PC and CCR to stack
4 Vector fetch
5 Instruction prefetch
6 Internal processing
Total
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after
prefetch.
4. The number of states increases if wait states are inserted in external memory access.

5.5 Usage Notes

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a
BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the
instant when execution of the instruction ends the interrupt is still enabled, so its interrupt
exception handling is carried out. If a higher-priority interrupt is also requested, however,
interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority
interrupt is ignored. This also applies to the clearing of an interrupt flag.
Figure 5-8 shows an example in which an IMIEA bit is cleared to 0 in the ITU's TIER.
On-Chip
Memory
2
*1
1 to 23
4
4
4
*2
4
*3
19 to 41
External Memory
8-Bit Bus
2 States 3 States
2 2
*1
1 to 27 1 to 31
8 12
8 12
8 12
4 4
31 to 57 43 to 73
*1
*4
*4
*4
*4
91