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= High
Exception handling state
Request for
End of
exception
exception
handling
handling
Program execution state
Notes: *1
From any state except hardware standby mode, a transition to the power-on reset
state occurs whenever
power-on reset state, a transition to the manual reset state occurs whenever
A transition can also be made to the reset state when the watchdog timer overflows.
*2
From any state, a transition to hardware standby mode occurs when
2.9
Usage Notes
2.9.1
Note on TAS Instruction Usage
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or
ER5 is used.
2.9.2
STM/LTM Instruction Usage
With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot
be used as a register that allows save (STM) or restore (LDM) operation.
With a single STM or LDM instruction, two to four registers can be saved or restored. The
available registers are as follows:
For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5
For three registers: ER0 to ER2, or ER4 to ER6
Reset state
= High
SLEEP instruction
goes low. From any state except hardware standby more or
Figure 2.13 State Transitions
*
1
= High,
= Low
Bus-released state
Bus
request
Program halt state
End of
bus request
*
2
goes low.
goes low.
Rev. 3.0, 10/02, page 53 of 686
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