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Exception -
handling state
RES = 1
Reset state
Notes: *1 A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode.
*2 A transition from any state to the hardware standby mode occurs when STBY goes Low.
3.6.1 Program Execution State
In this state the CPU executes program instructions.
3.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
(1) Saves the program counter and condition code register to the stack (except in the case of a
reset).
(2) Sets the interrupt mask (I) bit in the condition code register to "1."
(3) Fetches the start address of the exception-handling routine from the vector table.
(4) Branches to that address, returning to the program execution state.
See section 4, "Exception Handling," for further information on the exception-handling state.
Program
Exception
execution state
handling
request
Exception
handing
Interrupt request
NMI or IRQ
0
to IRQ
2
STBY=1, RES=0
Figure 3-12. State Transitions
52
SLEEP instruction
SLEEP
with SSBY bit set
instruction
Sleep mode
Software
standby mode
Hardware
standby mode
Power-down state
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