Transmit Data Register (Tdr)-H'ffdb; Serial Mode Register (Smr)-H'ffd8 - Hitachi H8/329 Series Hardware Manual

8.2.4 Transmit Data Register (TDR)—H'FFDB
Bit 7
Initial value 1
Read/Write R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted.
When the TSR becomes empty, the character written in the TDR is transferred to the TSR.
Continuous data transmission is possible by writing the next byte in the TDR while the current byte
is being transmitted from the TSR.
The TDR is initialized to H'FF at a reset and in the standby modes.
8.2.5 Serial Mode Register (SMR)—H'FFD8
Bit 7
C/A
Initial value 0
Read/Write R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H'00 at a reset and in the standby
modes. For further information on the SMR settings and communication formats, see tables 8-5
and 8-7 in section 8.3, "Operation."
Bit 7—Communication Mode (C/A): This bit selects the asynchronous or clocked synchronous
communication mode.
Bit 7
C/A Description
0 Asynchronous communication.
1 Clocked synchronous communication.
6 5 4
1 1 1
R/W R/W R/W
6 5 4
CHR PE O/E
0 0 0
R/W R/W R/W
167
3 2 1
1 1 1
R/W R/W R/W
3 2 1
STOP MP CKS1
0 0 0
R/W R/W R/W
0
1
R/W
0
CKS0
0
R/W
(Initial value)