Bus Cycles During Instruction Execution - Hitachi H8/300H Series Programming Manual

2.8 Bus Cycles During Instruction Execution

Table 2-8 indicates the bus cycles during instruction execution by the H8/300H CPU. For the
number of states per bus cycle, see table 2-7, Number of States per Cycle.
How to read the table:
Instruction
JMP @aa:24 R:W 2nd
Legend
R:B Byte-size read
R:W Word-size read
W:B Byte-size write
W:W Word-size write
2nd Address of 2nd word (3rd and 4th bytes)
3rd Address of 3rd word (5th and 6th bytes)
4th Address of 4th word (7th and 8th bytes)
5th Address of 5th word (9th and 10th bytes)
NEXT Address of next instruction
EA Effective address
VEC Vector address
1 2 3
Internal operation
R:W EA
(2 states)
Order of bus cycles
4 5
End of instruction
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
226
6 7 8