Dmac Bus Cycles (Dual Address Mode); Figure 7.16 Example Of Short Address Mode Transfer - Hitachi H8S/2215 Series Hardware Manual

7.4.9

DMAC Bus Cycles (Dual Address Mode)

Short Address Mode: Figure 7.16 shows a transfer example in which TEND
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
DMA read
φ
Address bus
*
Bus release

Figure 7.16 Example of Short Address Mode Transfer

A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND
which the transfer counter reaches 0.
Full Address Mode (Cycle Steal Mode): Figure 7.17 shows a transfer example in which
TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed
*
from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
Note: * TEND output cannot be used with this LSI.
Rev. 3.0, 10/02, page 182 of 686
DMA write DMA read
Bus release
output is enabled, TEND
*
DMA write DMA read DMA write
Bus release Last transfer cycle
output goes low in the transfer cycle in
*
output is enabled
*
DMA
dead
Bus release