Break On External Bus Cycle; Program Counter (Pc) Values Saved - Hitachi SH7095 Hardware User Manual

Table 6.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size Address Compared
Longword Compare break address register bits 31–2 to address bus bits 31–2
Word Compare break address register bits 31–1 to address bus bits 31–1
Byte Compare break address register bits 31–0 to address bus bits 31–0
3. When the data value is included in the break conditions on B channel:
When the data value is included in the break conditions, specify either longword. word or byte
as the operand size of the break bus cycle registers (BBRA, BBRB). When data values are
included in break conditions, a break interrupt is generated when the address conditions and
data conditions both match. To specify byte data for this case, set the same data in the two
bytes at bits 15–8 and bits 7–0 of the break data register B (BDRB) and break data mask
register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are
ignored.
6.3.4

Break on External Bus Cycle

1. Enable the external bus break enable bit (the EBBE bit of the BRCR) to generate a break for
the bus cycle generated by the external bus master when the bus is released. This can be done
with all masters and all slaves.
2. Address and read/write can be set for external buses, but size cannot be specified. Setting
sizes of byte/word/longword will be ignored. Also, no distinction can be made between
instruction fetch and data access for external bus cycles. All cycles are considered data access
cycles, so set 1 in bits IDA1 and IDB1 in BBRA and BBRB.
3. External input of addresses uses A26–A0, so set bits 31–27 of the break address registers
(BARA, BARB) to 0, or set bits 31–27 of the break address mask registers (BAMRA,
BAMRB) to 1 to mask the addresses not input.
4. When the conditions set for the external bus cycle are satisfied, the CMFPA and CMFPB bits
are set for the respective channels.
6.3.5

Program Counter (PC) Values Saved

1. Break on Instruction Fetch (Before Execution): The program counter (PC) value saved to the
stack in user break interrupt exception processing is the address that matches the break
condition. The user break interrupt is generated before the fetched instruction is executed. If a
break condition is set on an instruction that follows an interrupt-disabled instruction, however,
the break occurs before the execution of instruction that accepts the next interrupt is executed,
so the PC value saved is the address of the break.
2. Break on Instruction Fetch (After Execution): The program counter (PC) value saved to the
stack in user break interrupt exception processing is the address executed after the one that
matches the break condition. The fetched instruction is executed and the user break interrupt
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