Relation Between The Dmac, External Bus Requests, Refresh Cycles, And The Dtc; Figure 7.22 Example Of Multi-Channel Transfer; Table 7.9 Dmac Channel Priority Order - Hitachi H8S/2215 Series Hardware Manual

Table 7.9 DMAC Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the highest-
priority channel from among those issuing a request according to the priority order shown in table
7.14. During burst transfer, or when one block is being transferred in block transfer, the channel
will not be changed until the end of the transfer. Figure 7.22 shows a transfer example in which
transfer requests are issued simultaneously for channels 0A, 0B, and 1.
Address bus
DMA control Idle Read
Channel 0A
Request clear
Channel 0B
Channel 1
Bus
release
7.4.11

Relation between the DMAC, External Bus Requests, Refresh Cycles, and the DTC

There can be no break between a DMA cycle read and a DMA cycle write. This means that a
refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read
and external write in a DMA cycle.
Full Address Mode
Channel 0
Channel 1
DMA read DMA write
Write Idle
Request clear
Request Selection
hold
Request
Non-
selection
hold
Channel 0A Bus
transfer release

Figure 7.22 Example of Multi-Channel Transfer

DMA read DMA write
Read Write Idle
Request
Selection
hold
Channel 0B
transfer
Priority
High
Low
DMA read DMA write
Read Write
Request clear
Channel 1 transfer
Bus
release
Rev. 3.0, 10/02, page 187 of 686
DMA
read
Read