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6.1
Overview
The H8/3062 Series has an on-chip bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function that controls the operation of the internal bus
masters—the CPU can release the bus to an external device.
6.1.1
Features
The features of the bus controller are listed below.
• Manages external address space in area units
Manages the external space as eight areas (0 to 7) of 128 kbytes in 1-Mbyte modes, or 2
Mbytes in 16-Mbyte modes
Bus specifications can be set independently for each area
• Basic bus interface
Chip select (CS
8-bit access or 16-bit access can be selected for each area
Two-state access or three-state access can be selected for each area
Program wait states can be inserted for each area
Pin wait insertion capability is provided
• Idle cycle insertion
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted when an external read cycle is immediately followed by an
external write cycle
• Bus arbitration function
A built-in bus arbiter grants the bus right to the CPU, or an external bus master
• Other features
Choice of two address update modes (except H8/3062F-ZTAT)
Section 6 Bus Controller
to CS
) can be output for areas 0 to 7
0
7
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