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Pulse-Width Modulator for Motor Control (PWMMC)
12.9.2 PWM Counter Modulo Registers
The PWM counter modulus registers (PMODH and PMODL) hold a 12-bit unsigned number that
determines the maximum count for the up/down or up-only counter. In center-aligned mode, the PWM
period will be twice the modulus (assuming no prescaler). In edge-aligned mode, the PWM period will
equal the modulus. See
Address:
Read:
Write:
Reset:
Figure 12-35. PWM Counter Modulo Register High (PMODH)
Address:
Read:
Write:
Reset:
X = Indeterminate
Figure 12-36. PWM Counter Modulo Register Low (PMODL)
To avoid erroneous PWM periods, this value is buffered and will not be used by the PWM generator until
the LDOK bit has been set and the next PWM load cycle begins.
When reading this register, the value read is the buffer (not necessarily the
value the PWM generator is currently using).
Because of the equals-comparator architecture of this PWM, the
modulus = 0 case is considered illegal. Therefore, the modulus register is
not reset, and a modulus value of 0 will result in waveforms inconsistent
with the other modulus waveforms. If a modulus of 0 is loaded, the counter
will continually count down from $FFF. This operation will not be tested or
guaranteed (the user should consider it illegal). However, the dead-time
constraints and fault conditions will still be guaranteed.
144
Figure 12-35
and
Figure
$0028
Bit 7
6
5
0
0
0
0
0
0
= Unimplemented
$0029
Bit 7
6
5
Bit 7
Bit 6
Bit 5
X
X
X
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
12-36.
4
3
2
0
Bit 11
Bit 10
0
X
X
X = Indeterminate
4
3
2
Bit 4
Bit 3
Bit 2
X
X
X
NOTE
1
Bit 0
Bit 9
Bit 8
X
X
1
Bit 0
Bit 1
Bit 0
X
X
Freescale Semiconductor
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