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8.3.4.13
RCR Receive Exception Interrupt Enable (REIE) - Bit 20
When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set. When REIE is cleared, this interrupt
is disabled. Reading the SAISR status register followed by reading the enabled receivers data registers clears ROE, thus clearing the pending
interrupt.
8.3.4.14
RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21
The REDIE control bit is used to enable the receive even slot data interrupts. If REDIE is set, the receive even slot data interrupts are enabled.
If REDIE is cleared, the receive even slot data interrupts are disabled. A receive even slot data interrupt request is generated if REDIE is set
and the REDF status flag in the SAISR status register is set. Even time slots are all even-numbered time slots (0, 2, 4, etc.) when operating in
network mode. The zero time slot is marked by the frame sync signal and is considered to be even. Reading all the data registers of the enabled
receivers clears the REDF flag, thus servicing the interrupt.
Receive interrupts with exception have higher priority than receive even slot data interrupts, therefore if exception occurs (ROE is set) and
REIE is set, the ESAI requests an ESAI receive data with exception interrupt from the interrupt controller.
8.3.4.15
RCR Receive Interrupt Enable (RIE) - Bit 22
The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set. When RIE is cleared, this interrupt is disabled. Reading
the receive data registers of the enabled receivers clears RDF, thus clearing the interrupt.
Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if exception occurs (ROE is set) and REIE
is set, the ESAI requests an ESAI receive data with exception interrupt from the interrupt controller.
8.3.4.16
RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23
RLIE enables an interrupt after the last slot of a frame ended in network mode only. When RLIE is set the DSP is interrupted after the last slot
in a frame ended regardless of the receive mask register setting. When RLIE is cleared the receive last slot interrupt is disabled. Hardware and
software reset clear RLIE. RLIE is disabled when RDC[4:0]=00000 (on-demand mode). The use of the receive last slot interrupt is described
in
Section 8.4.3, ESAI Interrupt
8.3.5
ESAI Common Control Register (SAICR)
The read/write Common Control Register (SAICR) contains control bits for functions that affect both the receive and transmit sections of the
ESAI. See
Figure
8-10.
11
23
Hardware and software reset clear all the bits in the SAICR register. The ESAI SAICR register is located at x:$FFFFB4. The ESAI_1 SAICR
register is located at y:$FFFF94.
8.3.5.1
SAICR Serial Output Flag 0 (OF0) - Bit 0
The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin. When the ESAI is in the synchronous clock mode
(SYN=1), the SCKR pin is configured as the ESAI flag 0. If the receiver serial clock direction bit (RCKD) is set, the SCKR pin is the output
flag OF0, and data present in the OF0 bit is written to the OF0 pin at the beginning of the frame in normal mode or at the beginning of the
next time slot in network mode.
Freescale Semiconductor
Requests.
10
9
8
ALC
TEBE
22
21
20
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-10. SAICR Register
DSP56374 Users Guide, Rev. 1.2
7
6
5
4
SYN
19
18
17
16
ESAI Programming Model
3
2
1
0
OF2
OF1
OF0
15
14
13
12
8-23
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