STMicroelectronics STM32WL5 Series Reference Manual page 1236

Low-power universal asynchronous receiver transmitter (LPUART)
Bits 31:24 ADD[7:0]: Address of the LPUART node
These bits give the address of the LPUART node in Mute mode or a character code to be
recognized in low-power or Run mode:
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–
–
These bits can only be written when the reception is disabled (RE = 0) or when the USART is
disabled (UE = 0).
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 MSBFIRST: Most significant bit first
This bit is set and cleared by software.
0: data is transmitted/received with data bit 0 first, following the start bit.
1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
This bitfield can only be written when the LPUART is disabled (UE = 0).
Bit 18 DATAINV: Binary data inversion
This bit is set and cleared by software.
0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H).
The parity bit is also inverted.
This bitfield can only be written when the LPUART is disabled (UE = 0).
Bit 17 TXINV: TX pin active level inversion
This bit is set and cleared by software.
0: TX pin signal works using the standard logic levels (V
1: TX pin signal values are inverted (V
This enables the use of an external inverter on the TX line.
This bitfield can only be written when the LPUART is disabled (UE = 0).
Bit 16 RXINV: RX pin active level inversion
This bit is set and cleared by software.
0: RX pin signal works using the standard logic levels (V
1: RX pin signal values are inverted (V
This enables the use of an external inverter on the RX line.
This bitfield can only be written when the LPUART is disabled (UE = 0).
Bit 15 SWAP: Swap TX/RX pins
This bit is set and cleared by software.
0: TX/RX pins are used as defined in standard pinout
1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired
connection to another UART.
This bitfield can only be written when the LPUART is disabled (UE = 0).
Bit 14 Reserved, must be kept at reset value.
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In Mute mode: they are used in multiprocessor communication to wake up from Mute mode
with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter
should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used.
In low-power mode: they are used for wake up from low-power mode on character match.
When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up
from low-power mode is performed when the received character corresponds to the
character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit),
and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by
transmitter should be equal to 1.
In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus
protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF
flag is set on match. An interrupt is generated if the CMIE bit is set.
DD
= 0/mark, Gnd = 1/idle).
DD
DD
= 0/mark, Gnd = 1/idle).
DD
RM0453 Rev 5
= 1/idle, Gnd = 0/mark)
= 1/idle, Gnd = 0/mark)
RM0453