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7. Boot mode can be cleared by a reset. Cancel the reset*
at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT
overflow occurs.
8. Do not change the mode pin input levels in boot mode.
9. All interrupts are disabled during programming or erasing of the flash memory.
Notes: 1. Some parts of this area are reserved only for boot mode and therefore should not be
used for any other purpose.
2. After reset is cancelled, mode pin input settings must satisfy the mode programming
setup time (t
Table 18.5 Boot Mode Operation
Host Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
Receives data H'AA.
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order byte
following high-order byte).
Transmits 1-byte of programming control
program (repeated for N times).
Receives data H'AA.
= 4 states).
MDS
Communications Contents
H'00, H'00 . . . H'00
High-order byte and
Boot program
erase error
2
after driving the reset pin low, waiting
Branches to boot program at reset-start.
• Measures low-level period of receive data H'00.
• Calculates bit rate and sets it in BRR of SCI_1.
• Transmits data H'00 to host as adjustment end
H'00
indication.
H'55
H'AA
After receiving data H'55, transmits data
H'AA to host.
low-order byte
Echobacks the 2-byte data received to host.
Echoback
H'XX
Echobacks received data to host and also
Echoback
transfers it to RAM (repeated for N times).
H'FF
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'AA
H'FF to host and aborts operation.)
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Rev. 1.00, 05/04, page 443 of 544
LSI Operation
Processing Contents
Boot program start
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