Plls0 To Plls1 (S-Selector) (Input); Pllfoen (Pll Fo Output Enable) (Input) - Renesas PFESiP/V850EP1 User Manual

2.3.4 PLLS0 to PLLS1 (S-selector) (input)

Set the S-selector as below, according to the value of the PFD input frequency (fpfd) specified in Table 2-1 when
these pins are used in frequency diffusion mode.
PLL18
PLLS1
0
0
1
1

2.3.5 PLLFOEN (PLL FO output enable) (input)

The FO output of the internal PLL can be output from the PLLFO pin.
The IDLE control circuit is not stopped even in the IDLE mode, because it is on the CPU side.
FO is output to PLLFO only when a high level is input to PLLFOEN.
A low level is output when a low level is input to PLLFOEN.
This output control is an enable control configuration. Noise (whiskers) may occur when switching is performed
during an operation.
PLLFOEN
0
1
56
CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
Table 2-4. Setting the S-selector
PLL17
PLLS0
0 1.00 ≤ f < 1.20 (Open)
pfd
1.20 ≤ f < 1.45
1
pfd
1.45 ≤ f < 1.70
0
pfd
1.70 ≤ f ≤ 2.00
1
pfd
Table 2-5. PLL FO Output Control by PLLFOEN Pin
PLL FO Output Control
Low-level output
Output enabled
User's Manual A19069EJ2V0UM
PFD Input Frequency [MHz]