Timer Interrupt Enable Register (Tier) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

8.2.13 Timer Interrupt Enable Register (TIER)

TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel Abbreviation
0 TIER0
1 TIER1
2 TIER2
3 TIER3
4 TIER4
Bit
Initial value
Read/Write
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
220
Function
Enables or disables interrupt requests.
7 6
— —
1 1
— —
Reserved bits
5 4
— —
1 1
— —
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
3 2
— OVIE IMIEB
1 0
— R/W R/W
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
1 0
IMIEA
0 0
R/W