Interrupt Priority Registers A To G, I To K, M (Ipra To Iprg, Ipri To Iprk, Iprm) - Hitachi H8S/2215 Series Hardware Manual

5.3.1 Interrupt Priority Registers A to G, I to K, M (IPRA to IPRG, IPRI to IPRK,
IPRM)
The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a
value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of
the corresponding interrupt.
Bit Bit Name Initial Value R/W
7 – 0
6 IPR6 1
5 IPR5 1
4 IPR4 1
3 – 0
2 IPR2 1
1 IPR1 1
0 IPR0 1
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Description
– Reserved
These bits are always read as 0 and cannot be
modified.
R/W Sets the priority of the corresponding interrupt source.
R/W 000: Priority level 0 (Lowest)
R/W 001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
– Reserved
These bits are always read as 0 and cannot be
modified.
R/W Sets the priority of the corresponding interrupt source.
R/W 000: Priority level 0 (Lowest)
R/W 001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)