Timer Control/Status Registers (Tcsr); Table 11.2 Clock Input To Tcnt And Count Condition - Hitachi H8S/2215 Series Hardware Manual

Table 11.2 Clock Input to TCNT and Count Condition

Channel Bit 2
CKS2
TMR_0 0
1
TMR_1 0
1
All 1
Note: * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. This setting is
prohibited.
11.3.5

Timer Control/Status Registers (TCSR)

The TCSR registers display status flags, and control compare match output.
Rev. 3.0, 10/02, page 332 of 686
TCR
Bit 1 Bit 0
CKS1 CKS0
0 0
1
1 0
1
0 0
0 0
1
1 0
1
0 0
0 1
1 0
1 1
Description
Clock input disabled
Internal clock, counted at falling edge of ø/8
Internal clock, counted at falling edge of ø/64
Internal clock, counted at falling edge of ø/8192
Count at TCNT1 overflow signal*
Clock input disabled
Internal clock, counted at falling edge of ø/8
Internal clock, counted at falling edge of ø/64
Internal clock, counted at falling edge of ø/8192
Count at TCNT0 compare match A*
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling
edges