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14.2.2 Receive Data Register (RDR)—H'FFDD
Bit
Initial value
Read/Write
The RDR stores received data. As each character is received, it is transferred from the RSR to the
RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to
receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 at a reset and in the
standby modes.
14.2.3 Transmit Shift Register (TSR)
Bit
Read/Write
The TSR holds the character currently being transmitted. When transmission of this character is
completed, the next character is moved from the transmit data register (TDR) to the TSR and
transmission of that character begins. If the TDR does not contain valid data, the SCI stops
transmitting.
The CPU cannot read or write the TSR directly.
14.2.4 Transmit Data Register (TDR)—H'FFDB
Bit
Initial value
Read/Write
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted.
When the TSR becomes empty, the character written in the TDR is transferred to the TSR.
Continuous data transmission is possible by writing the next byte in the TDR while the current
byte is being transmitted from the TSR.
The TDR is initialized to H'FF at a reset and in the standby modes.
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7
6
5
0
0
0
R
R
R
7
6
5
—
—
—
7
6
5
1
1
1
R/W
R/W
R/W
4
3
0
0
R
R
R
4
3
—
—
—
4
3
1
1
R/W
R/W
R/W
248
2
1
0
0
0
0
R
R
2
1
0
—
—
2
1
0
1
1
1
R/W
R/W
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