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9.2.8
General Registers (GRA, GRB)
The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each
channel.
Channel
Abbreviation
0
GRA0, GRB0
1
GRA1, GRB1
2
GRA2, GRB2
Bit
15
Initial value
1
Read/Write
R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is
set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR.
When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current 16TCNT value is stored in
the general register. The corresponding IMFA or IMFB flag in TISRA/TISRB is set to 1 at the
same time. The valid edge or edges of the input capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are initialized to the output compare function (with no output signal) by a reset
and in standby mode. The initial value is H'FFFF.
14
13
12
11
1
1
1
1
R/W
R/W
R/W
R/W
R/W
Function
Output compare/input capture register
10
9
8
7
6
1
1
1
1
1
R/W
R/W
R/W
R/W
5
4
3
2
1
1
1
1
R/W
R/W
R/W
R/W
R/W
1
0
1
1
R/W
301
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