General Registers (Gra, Grb) - Hitachi H8/3022 Hardware Manual

TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and
an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM
mode and up-counters in other modes.
TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or
by input capture to GRA or GRB (counter clearing function) in the same channel.
When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in
the timer status register (TSR) of the corresponding channel.
When TCNT underflows (changes from H'0000 to H'FFFF), the overflow flag (OVF) is set to 1 in
TSR of the corresponding channel.
The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each TCNT is initialized to H'0000 by a reset and in standby mode.

8.2.8 General Registers (GRA, GRB)

The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.
Channel Abbreviation
0 GRA0, GRB0
1 GRA1, GRB1
2 GRA2, GRB2
3 GRA3, GRB3
4 GRA4, GRB4
Bit 15
Initial value 1
Read/Write R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in the timer I/O
control register (TIOR).
When a general register is used as an output compare register, its value is constantly compared
with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set
to 1 in the timer status register (TSR). Compare match output can be selected in TIOR.
Function
Output compare/input capture register
Output compare/input capture register; can be by buffer
registers BRA and BRB
14 13 12 11
1 1 1 1
R/W R/W R/W R/W
10 9 8 7
1 1 1 1
R/W R/W R/W R/W
6 5 4 3
1 1 1 1
R/W R/W R/W R/W
2 1 0
1 1 1
R/W R/W R/W
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