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Section 4. Basic Operation Timing; On-Chip Memory (Ram, Rom) - Hitachi H8/300L Series Programming Manual

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Section 4. Basic Operation Timing

CPU operation is synchronized by a clock (φ). The period from the rising edge of φ to the next
rising edge is called one state. A memory cycle or bus cycle consists of two or three states. For
details on access to on-chip memory and to on-chip peripheral modules see the applicable
hardware manual.
4.1

On-chip Memory (RAM, ROM)

Two-state access is employed for high-speed access to on-chip memory. The data bus width is
16 bits, allowing access in byte or word size. Figure 4-1 shows the on-chip memory access
cycle.
φ
Internal address bus
Internal read signal
Internal data bus*
(read access)
Internal write signal
Internal data bus*
(write access)
Note:
A 16-bit data bus is used making possible access to word-size
data in 2 states.
T
state
1
Figure 4-1. On-Chip Memory Access Cycle
Bus cycle
T
state
2
Address
Read data
Write data
151

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