Accessing Ordinary Space; Basic Timing - Hitachi SH7095 Hardware User Manual

Figure 7.5 32-Bit External Device and Their Access Units (Little Endian)
Figure 7.6 16-Bit External Device and Their Access Units (Little Endian)
7.4

Accessing Ordinary Space

7.4.1

Basic Timing

A strobe signal is output by ordinary space accesses of CS0–CS3 spaces to provide primarily for
SRAM direct connections. Figure 7.7 shows the basic timing of ordinary space accesses. Ordinary
accesses without waits end in 2 cycles. The BS signal is asserted for 1 cycle to indicate the start of
the bus cycle. The CSn signal is negated by the fall of clock T2 to ensure the negate period. The
negate period is thus half a cycle when accessed at the minimum pitch.
The access size is not specified during a read. The correct access start address will be output to the
LSB of the address, but since no access size is specified, the read will always be 32 bits for 32-bit
devices and 16 bits for 16-bit devices. For writes, only the WE signal of the byte that will be
written is asserted. For 32-bit devices, WE3 specifies writing to a 4n address and WE0 specifies
writing to a 4n+3 address. For 16-bit devices, WE1 specifies writing to a 2n address and WE0
specifies writing to a 2n+1 address. For 8-bit devices, only WE0 is used.
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