Execution Flow For Slave Cpu Synchronization - YASKAWA SVC User Manual

Slave I/O Register Configuration
Refer to the following section for details on register areas.
Information
OW
OW+1
OW+2
OW+3
OW+4
OW+5
OW+6
OW+7
6.6.5

Execution Flow for Slave CPU Synchronization

Power ON to Master
Confirmation That the Slave
CPU Is Synchronized
Detailed Information When an SVC Function Module Is Set as a Slave (page 7-16)
Output Registers
7 6 5 4 3 2 1 0
Reserved for system.
Command Control
Output Data 1 Low
High
Output Data 2 Low
High
Output Data 3 Low
High
Output Data 4 Low
High
Output Data 5 Low
High
Output Data 6 Low
High




6.6.5 Execution Flow for Slave CPU Synchronization

IW
IW+1
IW+2
IW+3
IW+4
IW+5
IW+6
IW+7
Operations on Slave
Power ON to Slave
Confirmation of Completion
of Slave Startup
SLVSC Control
Bit Turned ON
Confirmation of Completion of Slave
CPU Synchronization Preparations
SLVSC Control
Bit Turned OFF
Confirmation That the Slave
CPU Is Synchronized
6.6 Slave CPU Synchronization
Input Registers
7 6 5 4 3 2 1 0
Reserved for system.
Command Status
Input Data 1 Low
High
Input Data 2 Low
High
Input Data 3 Low
High
Input Data 4 Low
High
Input Data 5 Low
High
Input Data 6 Low
High



Procedure to Turn ON Power
(page 6-26)
Confirmation That the
Slave CPU Is Synchro-
nized (page 6-26)
6
6-25