Command Status - YASKAWA SVC User Manual

11.3.7

Command Status

This section describes the details of the Command Status register.
Bit 7
SYNC SYNCRDY
Bit 15
 D_ALM
• Definition
1: Device alarm
0: Any state other than the above
• Description
This bit shows when there is a device alarm in the I/O Module.
D_ALM changes to 1 when any device-specific alarm other than COMM_ALM or CMD_ALM
occurs.
When the Clear Alarms/Warnings command is executed or bit 3 (ALM_CLR) in the Command
Control register is set to 1, the I/O Module is restored to normal operation and D_ALM
changes back to 0.
 D_WAR
• Definition
1: Device warning
0: Any state other than the above
• Description
This bit shows when there is a device warning in the I/O Module.
D_WAR changes to 1 when any device-specific warning other than COMM_ALM or
CMD_ALM occurs.
When the Clear Alarms/Warnings command is executed or bit 3 (ALM_CLR) in the Command
Control register is set to 1, the I/O Module is restored to normal operation and D_WAR
changes back to 0.
 CMDRDY
• Definition
1: Commands can be received.
0: Any state other than the above
• Description
This bit shows when the I/O Module can receive I/O commands.
The I/O Module continues processing the current I/O command as long as the CMDRDY sta-
tus is 0. During this time, no new I/O commands can be executed. However, the Reset Com-
munications and Reset Network I/O commands are executed immediately, regardless of the
value of CMDRDY.
The amount of time that CMDRDY remains 0 depends on the product specifications of the I/
O Module. If the specified time is exceeded, bit 0 (TIMEOUT) in the Master Status register
changes to 1.
CMDRDY is 1 whenever a new I/O command can be executed, even if there is a current
alarm or warning.
 ALM_CLR_CMP
• Definition
1: ALM_CLR completed.
0: Any state other than the above
• Description
A value of 1 in ALM_CLR_CMP shows that the clear alarm process started via bit 3 (ALM_-
CLR) in the Command Control register has been completed.
To clear the status of ALM_CLR_CMP, set bit 3 (ALM_CLR) in the Command Control register
to 0.
Bit 6 Bit 5
SBUSY Reserved
Bit 14 Bit 13 Bit 12
COMM_ALM
11.3 MECHATROLINK-III I/O Module Settings
Bit 4 Bit 3 Bit 2
ALM_CLR
CMDRDY
_CMP
Bit 11 Bit 10
11.3.7 Command Status
Bit 1 Bit 0
D_WAR D_ALM
Bit 9 Bit 8
CMD_ALM
11
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