YASKAWA SVC User Manual page 454

7.2 MECHATROLINK Communications Settings
7.2.2 MECHATROLINK Detail Definition Dialog Box Details
 Output Register Configuration
Master
 Command Control
This section describes the details of the Command Control register.
Bit 7
Bit 15
• SLVSC
• Definition
1: Restarting prohibited.
0: Restarting allowed.
• Description
Specify whether slave CPU synchronization is automatically restarted when the slave CPU
changes from synchronized to asynchronized status.
If SLVSC is set to 1, slave CPU synchronization will not be restarted when the slave CPU
changes from synchronized to asynchronized status and operation will be continued in asyn-
chronized status
If SLVSC is set to 0, slave CPU synchronization is automatically restarted when the slave CPU
changes from synchronized to asynchronized status.
Refer to the following section for details on slave CPU synchronization.
6.6 Slave CPU Synchronization on page 6-18
7-18
MECHATROLINK
Transmission Path
7 6 5 4 3 2 1 0
00 hex
RCMD
01 hex
RWDT
02 hex
CMD_STAT
03 hex
04 hex
Data 1 Low
05 hex
High
06 hex
Data 2 Low
07 hex
High
08 hex
Data 3 Low
09 hex
High
0A hex
Data 4 Low
0B hex
High
0C hex
Data 5 Low
0D hex
High
0E hex
Data 6 Low
0F hex
High



Bit 6 Bit 5
Bit 14 Bit 13
OW+0
OW+1
OW+2
OW+3
OW+4
OW+5
OW+6
OW+7
Bit 4 Bit 3
Reserved
Bit 12 Bit 11
Reserved
Output Registers
for Slave
(SVC or SVC32)
7 6 5 4 3 2 1 0
Reserved for system.
Command Status
Data 1 Low
High
Data 2 Low
High
Data 3 Low
High
Data 4 Low
High
Data 5 Low
High
Data 6 Low
High



Bit 2 Bit 1
Bit 10 Bit 9
Bit 0
SLVSC
Bit 8