11.3.5 Command Control; 11.3.6 Master Status - YASKAWA SVC User Manual

11.3 MECHATROLINK-III I/O Module Settings

11.3.5 Command Control

11.3.5 Command Control
This section describes the details of the Command Control register.
Bit 7
Bit 15
 ALM_CLR: Clear Communications Alarm/Warning
• Definition
1: Clear alarms/warnings.
0: Disable clearing alarms/warnings.
• Description
The current alarms/warnings are cleared on the rising edge of this bit.
The same processing is performed for as the Clear Alarms/Warnings I/O command.

11.3.6 Master Status

This section describes the details of the Master Status register.
Bit 7
 TIMEOUT
• Definition
1: Command timeout detected.
0: Any state other than the above
• Description
This bit shows when execution of an I/O command is not completed within a specific period
of time (5 s).
Clear the alarm to restore operation.
 CYCLIC_INIT_ERR
• Definition
1: Cyclic communications initialization incomplete state detected.
0: Any state other than the above
• Description
This bit shows when the I/O Module fails to initialize cyclic communications.
Clear the alarm to restore operation.
 STATUS
• Definition
Value
0 hex
1 hex
2 hex
3 hex
4 hex
5 hex
• Description
These bits show the internal state of the I/O communications driver.
11-32
Bit 6 Bit 5
Reserve
Bit 14 Bit 13
Bit 6 Bit 5
STATUS
Meaning
Phase 0: The power supply is ON.
Phase 1: Status is initialized.
Phase 2: Communications are not synchronized.
Phase 3: Communications are synchronized.
Phase 4: Communications are stopped.
Phase 5: The power supply is OFF.
Bit 4 Bit 3
ALM_CLR
Bit 12 Bit 11
Reserve
Bit 4 Bit 3
CYCLIC_
INIT_ERR
Bit 2 Bit 1
Reserve
Bit 10 Bit 9
Bit 2 Bit 1
Reserve TIMEOUT
Bit 0
Bit 8
Bit 0