Timx Capture/Compare Register 1 (Timx_Ccr1); Timx Capture/Compare Register 2 (Timx_Ccr2) - ST STM32F207 Series Reference Manual

General-purpose timers (TIM2 to TIM5)
Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5).
Bits 15:0
14.4.13

TIMx capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5).
Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
14.4.14

TIMx capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38
Reset value: 0x0000 0000
31 30 29
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15 14 13
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430/1381
ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 14.3.1: Time-base unit
behavior.
The counter is blocked while the auto-reload value is null.
28 27 26 25
CCR1[31:16] (depending on timers)
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12 11 10 9
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If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.
28 27 26 25
CCR2[31:16] (depending on timers)
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12 11 10 9
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for more details about ARR update and
24 23 22
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8 7 6
CCR1[15:0]
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24 23 22
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8 7 6
CCR2[15:0]
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RM0033 Rev 9
21 20 19 18
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5 4 3 2
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21 20 19 18
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5 4 3 2
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RM0033
17 16
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1 0
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17 16
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1 0
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