Timx Capture/Compare Register 1 (Timx_Ccr1); Timx Capture/Compare Register 2 (Timx_Ccr2) - ST STM32L0x3 Reference Manual

RM0367
21.4.13

TIMx capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000
15 14 13
rw/r rw/r rw/r
Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
21.4.14

TIMx capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13
rw/r rw/r rw/r
Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
12 11 10 9
rw/r rw/r rw/r rw/r
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.
12 11 10 9
rw/r rw/r rw/r rw/r
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.
General-purpose timers (TIM2/TIM3)
8 7 6
CCR1[15:0]
rw/r rw/r rw/r
8 7 6
CCR2[15:0]
rw/r rw/r rw/r
RM0367 Rev 7
5 4 3 2
rw/r rw/r rw/r rw/r
5 4 3 2
rw/r rw/r rw/r rw/r
1 0
rw/r rw/r
1 0
rw/r rw/r
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