Interrupt Control Registers - Hitachi H8/3937 Series Hardware Manual

3.3.2

Interrupt Control Registers

Table 3-3 lists the registers that control interrupts.
Table 3-3 Interrupt Control Registers
Name
IRQ edge select register
Interrupt enable register 1
Interrupt enable register 2
Interrupt request register 1
Interrupt request register 2
Wakeup interrupt request register
Wakeup edge select register
Note: * Write is enabled only for writing of 0 to clear a flag.
1. IRQ edge select register (IEGR)
Bit 7
—
Initial value 1
Read/Write —
IEGR is an 8-bit read/write register used to designate whether pins IRQ
IRQ
signal used to interface to the FLEX™ decoder, are set to rising edge sensing or falling edge
0
sensing.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Bit 4: IRQ edge select (IEG4)
4
Bit 4 selects the input sensing of the IRQ
Bit 4
IEG4 Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Abbreviation
IEGR
IENR1
IENR2
IRR1
IRR2
IWPR
WEGR
6 5 4
— — IEG4
1 1 0
— — R/W
pin and ADTRG pin.
4
and ADTRG pin input is detected
4
and ADTRG pin input is detected
4
R/W Initial Value
R/W H'E0
R/W H'00
R/W H'00
R/W* H'20
R/W* H'00
R/W* H'00
R/W H'00
3 2
IEG3 IEG2
0 0
R/W R/W
to IRQ
4
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
H'FF90
1 0
IEG1 IEG0
0 0
R/W R/W
, and the internal
1
(initial value)
63