On-Chip Supporting Module Access Timing - Hitachi F-ZTAT H8/3039 Series Hardware Manual

ø
Address bus
AS
D
7
Figure 2-16 Pin States during On-Chip Memory Access

2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2-17 shows the on-chip supporting module
access timing. Figure 2-18 indicates the pin states.
ø
Internal address bus
Internal read signal
Read
access
Internal data bus
Internal write signal
Write
access
Internal data bus
Figure 2-17 Access Cycle for On-Chip Supporting Modules
, RD WR ,
to D
0
T
1
Address
High
High impedance
Bus cycle
T state
1
T
2
T state T state
2 3
Address
Read data
Write data
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