Tmdr-Timer Mode Register H'62 Itu (All Channels) - Hitachi H8/3035 Series Hardware Manual

TMDR—Timer Mode Register H'62
Bit 7
—
Initial value 1
Read/Write —
Flag direction
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1 OVF is set to 1 in TSR2 when TCNT2 overflows
Phase counting mode flag
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
456
ITU (all channels)
6 5 4
MDF FDIR PWM4
0 0 0
R/W R/W R/W
PWM mode 1
0 Channel 1 operates normally
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
PWM mode 3
0 Channel 3 operates normally
1 Channel 3 operates in PWM mode
PWM mode 4
0 Channel 4 operates normally
1 Channel 4 operates in PWM mode
3 2
PWM3 PWM2 PWM1
0 0
R/W R/W
PWM mode 0
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
1 0
PWM0
0 0
R/W R/W