Dma Terminal Control Register (Dmatcr) - Hitachi H8S/2338 Series Hardware Manual

Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits
8, 4, and 0 in DMABCR, by the DTC.
Bit 0
WE0A Description
0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled
1 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When
modifying these registers, the channel for which the modification is to be made should be halted.
5.4.2

DMA Terminal Control Register (DMATCR)

Bit :
—
Initial value :
R/W : —
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC
transfer end pin output. A port can be set for output automatically, and a transfer end signal output,
by setting the appropriate bit.
DMATCR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.
Bit 5
TEE1 Description
TEND1 pin output disabled
0
TEND1 pin output enabled
1
144
7 6
— TEE1
0 0
— R/W
5 4
TEE0 —
0 0
R/W —
3 2
— —
0 0
— —
(Initial value)
1 0
—
0 0
—
(Initial value)