Valid Strobes; Figure 6.8 Access Sizes And Data Alignment Control (16-Bit Access Area); Table 6.4 Data Buses Used And Valid Strobes - Hitachi H8/3062 Hardware Manual

In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Byte size
Byte size
Word size
Longword size

Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area)

6.4.3

Valid Strobes

Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.4 Data Buses Used and Valid Strobes
Access
Area Size
8-bit access Byte
area
16-bit access Byte
area
Word
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
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· Even address
· Odd address
1st bus cycle
2nd bus cycle
Read/
Write Address
Read —
Write —
Read Even
Odd
Write Even
Odd
Read —
Write —
Upper data bus
D D
15 8
Valid Upper Data Bus
Strobe (D to D )
15 8
RD
Valid
HWR
RD
Valid
Invalid
HWR
Valid
LWR
Undetermined data Valid
RD
Valid
HWR,
Valid
LWR
Lower data bus
D D
7 0
Lower Data Bus
(D to D )
7 0
Invalid
Undetermined data
Invalid
Valid
Undetermined data
Valid
Valid