Valid Strobes - Hitachi H8/3006 Hardware Manual

In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Byte size
Byte size
Word size
Longword size
Figure 6.6 Access Sizes and Data Alignment Control (16-Bit Access Area)
6.4.3

Valid Strobes

Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
· Even address
· Odd address
1st bus cycle
2nd bus cycle
Upper data bus
D D D
15 8
Lower data bus
D
7 0
133