Table of Contents
Advertisement
12.3.1
Next Data Enable Registers H, L (NDERH, NDERL)
NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a
bit-by-bit basis. The corresponding DDR also needs to be set to 1 in order to enable pulse output
by the PPG.
• NDERH
Bit
Bit Name
7
NDER15
6
NDER14
5
NDER13
4
NDER12
3
NDER11
2
NDER10
1
NDER9
0
NDER8
• NDERL
Bit
Bit Name
7
NDER7
6
NDER6
5
NDER5
4
NDER4
3
NDER3
2
NDER2
1
NDER1
0
NDER0
Rev. 1.0, 09/02, page 266 of 568
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Next Data Enable 8 to 15
When a bit is set to 1 for pulse output by NDRH,
the value in the corresponding NDRH bit is
transferred to the PODRH bit by the selected
output trigger. Values are not transferred from
NDRH to PODRH for cleared bits.
Description
Next Data Enable 0 to 7
When a bit is set to 1 for pulse output by NDRL, the
value in the corresponding NDRL bit is transferred
to the PODRL bit by the selected output trigger.
Values are not transferred from NDRL to PODRL
for cleared bits.
Advertisement
Table of Contents
