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4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state ends. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
4.3 Interrupts
Interrupt exception handling can be requested by five external sources (NMI, IRQ
IRQ
) and 25 internal sources in the on-chip supporting modules. Figure 4-3 classifies the interrupt
5
sources and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
integrated timer unit (ITU), serial communication interface (SCI), and A/D converter. Each
interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Notes:
Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates
Figure 4-3 Interrupt Sources and Number of Interrupts
78
External interrupts
Interrupts
Internal interrupts
an interrupt request at every counter overflow.
NMI (1)
IRQ , IRQ , IRQ , IRQ (4)
0
1
4
WDT* (1)
ITU (15)
SCI (8)
A/D converter (1)
, IRQ
, IRQ
,
0
1
4
5
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