ST STM32L4x6 Reference Manual page 1473

RM0351
Bit 4 SLAKI
Note: When SLKIE=0, no polling on SLAKI is possible. In this case the SLAK bit can be
Bit 3 WKUI
Bit 2 ERRI
Bit 1 SLAK
Note: The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR
Bit 0 INAK
CAN transmit status register (CAN_TSR)
Address offset: 0x08
Reset value: 0x1C00 0000
31 30 29
LOW2 LOW1 LOW0 TME2
r r r
15 14 13
ABRQ1 Res. Res.
rs
:
Sleep acknowledge interrupt
When SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered Sleep
Mode. When set, this bit generates a status change interrupt if the SLKIE bit in the
CAN_IER register is set.
This bit is cleared by software or by hardware, when SLAK is cleared.
polled.
:
Wakeup interrupt
This bit is set by hardware to signal that a SOF bit has been detected while the CAN
hardware was in Sleep mode. Setting this bit generates a status change interrupt if the
WKUIE bit in the CAN_IER register is set.
This bit is cleared by software.
:
Error interrupt
This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and
the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status
change interrupt if the ERRIE bit in the CAN_IER register is set.
This bit is cleared by software.
:
Sleep acknowledge
This bit is set by hardware and indicates to the software that the CAN hardware is now in
Sleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP
bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left Sleep mode (to be
synchronized on the CAN bus). To be synchronized the hardware has to monitor a
sequence of 11 consecutive recessive bits on the CAN RX signal.
register is cleared. Please refer to the AWUM bit of the CAN_MCR register description
for detailed information for clearing SLEEP bit
:
Initialization acknowledge
This bit is set by hardware and indicates to the software that the CAN hardware is now in
initialization mode. This bit acknowledges the initialization request from the software (set
INRQ bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left the initialization mode (to
be synchronized on the CAN bus). To be synchronized the hardware has to monitor a
sequence of 11 consecutive recessive bits on the CAN RX signal.
28 27 26
TME1 TME0
r r r
12 11 10
Res. TERR1 ALST1 TXOK1
rc_w1 rc_w1 rc_w1
25 24 23 22
CODE[1:0] ABRQ2 Res.
r r rs
9 8 7 6
RQCP1 ABRQ0 Res.
rc_w1 rs
DocID024597 Rev 3
Controller area network (bxCAN)
21 20 19 18
Res. Res. TERR2 ALST2
rc_w1 rc_w1
5 4 3 2
Res. Res. TERR0 ALST0
rc_w1 rc_w1
17 16
TXOK2 RQCP2
rc_w1 rc_w1
1 0
TXOK0 RQCP0
rc_w1 rc_w1
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